WM8191

Advanced Information

WOLFSON MICROELECTRONICS LTD

AI Rev 3.1 April 2001

2

PIN CONFIGURATION

ORDERING INFORMATION

DEVICE

TEMP. RANGE

PACKAGE

XWM8191CFT

0 to 70

°C

48-pin TQFP

1mm thick body

37

47 46 45 44 43 42 41 40 39 38

48

VRX

AGND3

GINP

AGND2

BINP

AGND1

VRLC/VBIAS

RINP

AGND4

DVDD1

OEB

SEN/STB

DGND4

DGND3

OP[7]

OP[8]

OP[9]

OP[10]

DVDD3

DGND2

OP[3]

OP[4]

OP[5]

OP[6]

25

31

30

29

28

27

26

36

35

34

33

32

1

9

8

7

6

5

4

3

2

12

11

10

24

23

16 17 18 19 20 21 22

13 14 15

PIN DESCRIPTION

PIN

NAME

TYPE

DESCRIPTION

1

VRX

Analogue output

Input return bias voltage.

This pin must be decoupled to AGND via a capacitor.

2

VRLC/VBIAS

Analogue I/O

Selectable analogue output voltage for RLC or single-ended bias reference.

This pin would typically be decoupled to AGND via a capacitor.

VRLC can be externally driven if programmed Hi-Z.

3

AGND1

Supply

Analogue ground (0V).

4

BINP

Analogue input

Blue channel input video.

5

AGND2

Supply

Analogue ground (0V).

6

GINP

Analogue input

Green channel input video.

7

AGND3

Supply

Analogue ground (0V).

8

RINP

Analogue input

Red channel input video.

9

AGND4

Supply

Analogue ground (0V).

10

DVDD1

Supply

Digital supply (5V) for logic and clock generator. This must be operated at the same

potential as AVDD.

11

OEB

Digital input

Output Hi-Z control, all digital outputs disabled when OEB = 1.

Serial interface: enable pulse, active high

Parallel interface: strobe, active low

12

SEN/STB

Digital input

Latched on NRESET rising edge: if Low then device control is via serial interface,

if high then device control is via parallel interface.

13

SDI/DNA

Digital input

Serial interface: serial input data signal

Parallel interface:

High = data, Low = address

14

SCK/RNW

Digital input

Serial interface: serial clock signal

Parallel interface:

High: OP[13:6] is output bus.

Low: OP[13:6] is input bus (Hi-Z).

15

VSMP

Digital input

Video sample synchronisation pulse.

16

RLC/ACYC

Digital input

RLC (active high) selects reset level

clamp on a pixel-by-pixel basis – tie high

if used on every pixel.

ACYC autocycles between R, G, B

inputs when in Line-by-Line mode.

17

MCLK

Digital input

Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or

any multiple of 2 thereafter depending on input sample mode).

18

DGND1

Supply

Digital ground (0V).

19

NC

No connection.

20

NC

No connection.