CS43L22 datasheet(16/66 Pages) CIRRUS

16 / 66 page

DS792F2

CS43L22

Confidential Draft

3/4/10

SWITCHING SPECIFICATIONS - SERIAL PORT

Inputs: Logic 0 = DGND; Logic 1 = VL.

11. After powering up the CS43L22, RESET should be held low after the power supplies and clocks are

settled.

12. See “Example System Clock Frequencies” on page 61 for typical MCLK frequencies.

Parameters

Symbol

Min

Max

Units

RESET pin Low Pulse Width

(Note 11)

MCLK Frequency (Note 12)

(See “Serial Port Clock-

ing” on page 29)

MHz

MCLK Duty Cycle

Slave Mode

Sample Rate (LRCK)

(See “Serial Port Clock-

ing” on page 29)

kHz

LRCK Duty Cycle

SCLK Frequency

1/tP

-64•Fs

SCLK Duty Cycle

LRCK Setup Time Before SCLK Rising Edge

ts(LK-SK)

SDIN Setup Time Before SCLK Rising Edge

ts(SD-SK)

SDIN Hold Time After SCLK Rising Edge

Master Mode

Sample Rate (LRCK)

(See “Serial Port Clock-

ing” on page 29)

LRCK Duty Cycle

SCLK Frequency

SCLK=MCLK mode

1/tP

12.0000

MHz

MCLK=12.0000 MHz

1/tP

-68•Fs

all other modes

1/tP

-64•Fs

SCLK Duty Cycle

SDIN Setup Time Before SCLK Rising Edge

ts(SD-SK)

SDIN Hold Time After SCLK Rising Edge

ts(SD-SK)

MSB

MSB-1

LRCK

SCLK

SDIN

ts(LK-SK)

Figure 3. Serial Audio Interface Timing

CS43L22 数据表(PDF) 16 Page - Cirrus Logic

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