TMP320C6720RFP300 datasheet(84/118 Pages) TI

84 / 118 page

4.14.2 SPI Peripheral Registers Description(s)

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

www.ti.com

Table 4-26 is a list of the SPI registers.

Table 4-26. SPIx Configuration Registers

SPI0

SPI1

DESCRIPTION

BYTE ADDRESS

0x4700 0000

0x4800 0000

SPIGCR0

Global Control Register 0

0x4700 0004

0x4800 0004

SPIGCR1

Global Control Register 1

0x4700 0008

0x4800 0008

SPIINT0

Interrupt Register

0x4700 000C

0x4800 000C

SPILVL

Interrupt Level Register

0x4700 0010

0x4800 0010

SPIFLG

Flag Register

0x4700 0014

0x4800 0014

SPIPC0

Pin Control Register 0 (Pin Function)

0x4700 0018

0x4800 0018

SPIPC1

Pin Control Register 1 (Pin Direction)

0x4700 001C

0x4800 001C

SPIPC2

Pin Control Register 2 (Pin Data In)

0x4700 0020

0x4800 0020

SPIPC3

Pin Control Register 3 (Pin Data Out)

0x4700 0024

0x4800 0024

SPIPC4

Pin Control Register 4 (Pin Data Set)

0x4700 0028

0x4800 0028

SPIPC5

Pin Control Register 5 (Pin Data Clear)

0x4700 002C

0x4800 002C

Reserved

Reserved - Do not write to this register

0x4700 0030

0x4800 0030

Reserved

Reserved - Do not write to this register

0x4700 0034

0x4800 0034

Reserved

Reserved - Do not write to this register

0x4700 0038

0x4800 0038

SPIDAT0

Shift Register 0 (without format select)

0x4700 003C

0x4800 003C

SPIDAT1

Shift Register 1 (with format select)

0x4700 0040

0x4800 0040

SPIBUF

Buffer Register

0x4700 0044

0x4800 0044

SPIEMU

Emulation Register

0x4700 0048

0x4800 0048

SPIDELAY

Delay Register

0x4700 004C

0x4800 004C

SPIDEF

Default Chip Select Register

0x4700 0050

0x4800 0050

SPIFMT0

Format Register 0

0x4700 0054

0x4800 0054

SPIFMT1

Format Register 1

0x4700 0058

0x4800 0058

SPIFMT2

Format Register 2

0x4700 005C

0x4800 005C

SPIFMT3

Format Register 3

0x4700 0060

0x4800 0060

TGINTVECT0

Interrupt Vector for SPI INT0

0x4700 0064

0x4800 0064

TGINTVECT1

Interrupt Vector for SPI INT1

Peripheral and Electrical Specifications

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