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S

1

2

8

9

NACK

ACK

Data Output

by Transmitter

Data Output

by Receiver

SCL From

Master

Start

Condition

Clock Pulse for

Acknowledgment

Device Address

1

0

0

0

0

1

1

Fixed Slave Address

R/W

Control Register and Command Byte

TCA6507

WITH INTENSITY CONTROL AND SHUTDOWN

SCPS164B – MAY 2007 – REVISED NOVEMBER 2007

Table 1. Interface Definition

BIT

BYTE

7 (MSB)

6

5

4

3

2

1

0 (LSB)

1

0

0

0

1

0

1

R/W

Px I/O data bus

P6

P5

P4

P3

P2

P1

P0

(1)

X = Don't care

The address of the TCA6507 is shown in Figure 5.

Figure 5. TCA6507 Address

The last bit of the slave address defines the operation (read or write) to be performed. High (1) selects a read

operation, and low (0) selects a write operation.

Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is

stored in the control register. The last four bits (B0, B1, B2 and B3) of this command byte determine the internal

registers (Select0, Select1, Select2, Fade-On Time, Fully-On Time, Fade-Off Time, First Fully-Off Time, Second

Fully-Off Time, Maximum Intensity and Initialization) that are affected. The command byte is sent only during a

write transmission.

6

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Product Folder Link(s): TCA6507