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MCP4901-E/MS 数据表(PDF) 23 Page - Microchip Technology |
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MCP4901-E/MS 数据表(HTML) 23 Page - Microchip Technology |
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23 / 50 page ![]() 2010 Microchip Technology Inc. DS22248A-page 23 MCP4901/4911/4921 5.0 SERIAL INTERFACE 5.1 Overview The MCP4901/4911/4921 devices are designed to interface directly with the Serial Peripheral Interface (SPI) port, which is available on many microcontrollers and supports Mode 0,0 and Mode 1,1. Commands and data are sent to the device via the SDI pin, with data being clocked-in on the rising edge of SCK. The communications are unidirectional, thus the data cannot be read out of the MCP4901/4911/4921. The CS pin must be held low for the duration of a write command. The write command consists of 16 bits and is used to configure the DAC’s control and data latches. Register 5-1 through Register 5-3 detail the input regis- ter that is used to configure and load the DAC register for each device. Figure 5-1 through Figure 5-3 show the write command for each device. Refer to Figure 1-1 and the SPI Timing Specifications Table for detailed input and output timing specifications for both Mode 0,0 and Mode 1,1 operation. 5.2 Write Command The write command is initiated by driving the CS pin low, followed by clocking the four Configuration bits and the 12 data bits into the SDI pin on the rising edge of SCK. The CS pin is then raised, causing the data to be latched into the DAC’s input register. The MCP4901/4911/4921 utilizes a double-buffered latch structure to allow the analog output to be synchronized with the LDAC pin, if desired. By bringing the LDAC pin down to a low state, the con- tent stored in the DAC’s input register is transferred into the DAC’s output register (VOUT), and VOUT is updated. All writes to the MCP4901/4911/4921 devices are 16-bit words. Any clocks past the 16th clock will be ignored. The Most Significant 4 bits are Configuration bits. The remaining 12 bits are data bits. No data can be transferred into the device with CS high. This transfer will only occur if 16 clocks have been transferred into the device. If the rising edge of CS occurs prior to that, shifting of data into the input register will be aborted. |
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