GTL2002_7

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 07 — 2 July 2009

4 of 22

NXP Semiconductors

GTL2002

2-bit bidirectional low voltage translator

6.2 Pin description

7.

Functional description

Refer to Figure 1 “Functional diagram”.

7.1 Function selection

[1]

GREF should be at least 1.5 V higher than SREF for best translator operation.

[2]

Sn is not pulled up or pulled down.

[3]

Sn follows the Dn input LOW.

[4]

[1]

GREF should be at least 1.5 V higher than SREF for best translator operation.

[2]

[3]

Dn follows the Sn input LOW.

[4]

Table 3.

Pin description

Symbol

Pin

Description

SO8, TSSOP8,

XQFN8U

VSSOP8

GND

1

4

ground (0 V)

SREF

2

1

source of reference transistor

S1

3

2

port S1

S2

4

3

port S2

D2

5

5

port D2

D1

6

6

port D1

DREF

7

7

drain of reference transistor

GREF

8

8

gate of reference transistor

Table 4.

Function selection, HIGH to LOW translation

Assuming Dn is at the higher voltage level.

H = HIGH voltage level; L = LOW voltage level; X = Don’t care.

GREF[1]

DREF

SREF

Input Dn

Output Sn

Transistor

HH0 V

X

X

off

HHVTT[4]

on

HHVTT[4]

LL[3]

on

LL0 V

X

X

off

Table 5.

Function selection, LOW to HIGH translation

Assuming Dn is at the higher voltage level.

H = HIGH voltage level; L = LOW voltage level; X = Don’t care.

GREF[1]

DREF

SREF

Input Sn

Output Dn

Transistor

HH0 V

X

X

off

HHVTT[4]

H[2]

nearly off

HHVTT[4]

LL[3]

on

LL0 V

X

X

off