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GTL2002D 数据表(PDF) 6 Page - NXP Semiconductors |
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GTL2002D 数据表(HTML) 6 Page - NXP Semiconductors |
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6 / 22 page ![]() GTL2002_7 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 07 — 2 July 2009 6 of 22 NXP Semiconductors GTL2002 2-bit bidirectional low voltage translator 8.2 Unidirectional down translation For unidirectional clamping, higher voltage to lower voltage, the GREF input must be connected to DREF and both pins pulled to the higher side VCC through a pull-up resistor (typically 200 k Ω). A filter capacitor on DREF is recommended. Pull-up resistors are required if the chip set I/O are open-drain. The opposite side of the reference transistor (SREF) is connected to the processor core supply voltage. When DREF is connected through a 200 k Ω resistor to a 3.3 V to 5.5 V V CC supply and SREF is set between 1.0 V to (VCC − 1.5 V), the output of each Sn has a maximum output voltage equal to SREF. 8.3 Unidirectional up translation For unidirectional up translation, lower voltage to higher voltage, the reference transistor is connected the same as for a down translation. A pull-up resistor is required on the higher voltage side (Dn or Sn) to get the full HIGH level, since the GTL-TVC device will only pass the reference source (SREF) voltage as a HIGH when doing an up translation. The driver on the lower voltage side only needs pull-up resistors if it is open-drain. Typical unidirectional HIGH-to-LOW voltage translation. Fig 7. Unidirectional down translation to protect low voltage processor pins GREF DREF 002aac061 D1 D2 200 k Ω CHIPSET I/O VCC 5 V GND SREF S1 S2 CPU I/O VCORE 1.8 V 1.5 V 1.2 V 1.0 V totem pole I/O easy migration to lower voltage as processor geometry shrinks Typical unidirectional LOW-to-HIGH voltage translation. Fig 8. Unidirectional up translation to higher voltage chip sets GREF DREF 002aac062 D1 D2 200 k Ω CHIPSET I/O VCC 5 V GND SREF S1 S2 CPU I/O VCORE 1.8 V 1.5 V 1.2 V 1.0 V easy migration to lower voltage as processor geometry shrinks totem pole I/O or open-drain |
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