LPC2129 datasheet(22/44 Pages) NXP

22 / 44 page

LPC2109_2119_2129_6

Product data sheet

Rev. 06 — 10 December 2007

22 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

CRP1 disables access to chip via the JTAG and allows partial ﬂash update (excluding

ﬂash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is

required and ﬂash ﬁeld updates are needed but all sectors can not be erased.

CRP2 disables access to chip via the JTAG and only allows full ﬂash erase and update

using a reduced set of the ISP commands.

Running an application with level CRP3 selected fully disables any access to chip via the

JTAG pins and the ISP. This mode effectively disables ISP override using P0[14] pin, too. It

is up to the user’s application to provide (if needed) ﬂash update mechanism using IAP

calls or call reinvoke ISP command to enable ﬂash update via UART0.

Remark: Devices without the sufﬁx /00 or /01 have only a security level equivalent to

CRP2 available.

6.18.5 External interrupt inputs

The LPC2109/2119/2129 include up to nine edge or level sensitive External Interrupt

Inputs as selectable pin functions. When the pins are combined, external events can be

processed as four independent interrupt signals. The External Interrupt Inputs can

optionally be used to wake up the processor from Power-down mode.

6.18.6 Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip

ﬂash memory, or to the on-chip static RAM. This allows code running in different memory

spaces to have control of the interrupts.

6.18.7 Power control

The LPC2109/2119/2129 support two reduced power modes: Idle mode and Power-down

mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt

occurs. Peripheral functions continue operation during Idle mode and may generate

interrupts to cause the processor to resume execution. Idle mode eliminates power used

by the processor itself, memory systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.

The processor state and registers, peripheral registers, and internal SRAM values are

preserved throughout Power-down mode and the logic levels of chip output pins remain

static. The Power-down mode can be terminated and normal operation resumed by either

a Reset or certain speciﬁc interrupts that are able to function without clocks. Since all

dynamic operation of the chip is suspended, Power-down mode reduces chip power

consumption to nearly zero.

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

LPC2129 数据表(PDF) 22 Page - NXP Semiconductors

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