LPC2129 datasheet(14/44 Pages) NXP

14 / 44 page

LPC2109_2119_2129_6

Product data sheet

Rev. 06 — 10 December 2007

14 of 44

NXP Semiconductors

LPC2109/2119/2129

Single-chip 16/32-bit microcontrollers

[1]

SSP interface available on LPC2109/01, LPC2119/01, and LPC2129/01 only.

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Conﬁguration registers control the multiplexers to allow connection between the

pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins

prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any

enabled peripheral function that is not mapped to a related pin should be considered

undeﬁned.

6.7 General purpose parallel I/O (GPIO) and Fast I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

parallel I/O registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

6.7.1 Features

• Bit-level set and clear registers allow a single instruction set or clear of any number of

bits in one port.

• Direction control of individual bits.

• Separate control of output set and clear.

• All I/O default to inputs after reset.

6.7.2 Features added with the Fast GPIO set of registers available on

LPC2109/2119/2129/01 only

• Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O

timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All Fast GPIO registers are byte addressable.

• Entire port value can be written in one instruction.

• Ports are accessible via either the legacy group of registers (GPIOs) or the group of

registers providing accelerated port access (Fast GPIOs).

System Control

External Interrupt 0 (EINT0)

External Interrupt 1 (EINT1)

External Interrupt 2 (EINT2)

External Interrupt 3 (EINT3)

ADC

A/D Converter

CAN

CAN1, CAN2 and Acceptance Filter

19 to 23

Table 4.

Interrupt sources …continued

Block

Flag(s)

VIC channel #

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