LPC2104FBD48SLASH01 datasheet(16/41 Pages) NXP

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LPC2104_2105_2106_7

Product data sheet

Rev. 07 — 20 June 2008

16 of 41

NXP Semiconductors

LPC2104/2105/2106

Single-chip 32-bit microcontrollers

6.9 General purpose parallel I/O

Device pins that are not connected to a speciﬁc peripheral function are controlled by the

GPIO registers. Pins may be dynamically conﬁgured as inputs or outputs. Separate

registers allow setting or clearing any number of outputs simultaneously. The value of the

output register may be read back, as well as the current state of the port pins.

6.9.1 Features

• Direction control of individual bits.

• Separate control of output set and clear.

• All I/O default to inputs after reset.

6.9.2 Features added with the Fast GPIO set of registers available on

LPC2104/2105/2106/01 only

• Fast GPIO registers are relocated to the ARM local bus for the fastest possible I/O

timing, enabling port pin toggling up to 3.5 times faster than earlier LPC2000 devices.

• Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

• All Fast GPIO registers are byte addressable.

• Entire port value can be written in one instruction.

• Ports are accessible via either the legacy group of registers (GPIOs) or the group of

registers providing accelerated port access (Fast GPIOs).

6.10 UARTs

The LPC2104/2105/2106 each contain two UARTs. One UART provides a full modem

control handshake interface, the other provides only transmit and receive data lines.

6.10.1 Features

• 16 byte Receive and Transmit FIFOs

• Register locations conform to 16C550 industry standard

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B

• Built-in baud rate generator

25:24

P0.28

GPIO Port 0.28

TMS

27:26

P0.29

GPIO Port 0.29

TCK

29:28

P0.30

GPIO Port 0.30

TDI

31:30

P0.31

GPIO Port 0.31

TDO

Table 7.

Pin function select register 1 (PINSEL1 - 0xE002 C004) …continued

PINSEL1

Pin name

Value

Function

Value after

reset

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