LPC2104FBD48SLASH01 datasheet(24/41 Pages) NXP

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LPC2104_2105_2106_7

Product data sheet

Rev. 07 — 20 June 2008

24 of 41

NXP Semiconductors

LPC2104/2105/2106

Single-chip 32-bit microcontrollers

processor clock rate. The second purpose of the APB divider is to allow power savings

when an application does not require any peripherals to run at the full processor rate.

Because the APB divider is connected to the PLL output, the PLL remains active (if it was

running) during Idle mode.

6.19 Emulation and debugging

The LPC2104/2105/2106 support emulation and debugging via a JTAG serial port. A trace

port allows tracing program execution. Each of these functions requires a trade-off of

debugging features versus device pins. Because the LPC2104/2105/2106 are provided in

a small package, there is no room for permanently assigned JTAG or Trace pins. An

alternate JTAG port allows an option to debug functions assigned to the pins used by the

primary JTAG port (see Section 6.8).

6.19.1 EmbeddedICE

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of

the target system requires a host computer running the debugger software and an

EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote

Debug Protocol commands to the JTAG data needed to access the ARM core.

The ARM core has a Debug Communication Channel function built-in. The debug

communication channel allows a program running on the target to communicate with the

host debugger or another separate host without stopping the program ﬂow or even

entering the debug state. The debug communication channel is accessed as a

co-processor 14 by the program running on the ARM7TDMI-S core. The debug

communication channel allows the JTAG port to be used for sending and receiving data

without affecting the normal program ﬂow. The debug communication channel data and

control registers are mapped in to addresses in the EmbeddedICE logic.

The JTAG clock (TCK) must be slower than 1

⁄

6 of the CPU clock (CCLK) for the JTAG

interface to operate.

6.19.2 Embedded trace

Since the LPC2104/2105/2106 have signiﬁcant amounts of on-chip memory, it is not

possible to determine how the processor core is operating simply by observing the

external pins. The Embedded Trace Macrocell (ETM) provides real-time trace capability

for deeply embedded processor cores. It outputs information about processor execution to

the trace port.

The ETM is connected directly to the ARM core and not to the main AMBA system bus. It

compresses the trace information and exports it through a narrow trace port. An external

trace port analyzer must capture the trace information under software debugger control.

Instruction trace (or PC trace) shows the ﬂow of execution of the processor and provides a

list of all the instructions that were executed. Instruction trace is signiﬁcantly compressed

by only broadcasting branch addresses as well as a set of status signals that indicate the

pipeline status on a cycle by cycle basis. Trace information generation can be controlled

by selecting the trigger resource. Trigger resources include address comparators,

counters and sequencers. Since trace information is compressed the software debugger

requires a static image of the code being executed. Self-modifying code cannot be traced

because of this restriction.

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