LPC2104FBD48SLASH01 datasheet(20/41 Pages) NXP

20 / 41 page

LPC2104_2105_2106_7

Product data sheet

Rev. 07 — 20 June 2008

20 of 41

NXP Semiconductors

LPC2104/2105/2106

Single-chip 32-bit microcontrollers

• Programmable 32-bit timer with internal pre-scaler.

• Selectable time period from (Tcy(PCLK) × 256 × 4) to (Tcy(PCLK) × 232 × 4) in multiples of

Tcy(PCLK) × 4.

6.16 Real time clock

The Real Time Clock (RTC) is designed to provide a set of counters to measure time

when normal or idle operating mode is selected. The RTC has been designed to use little

power, making it suitable for battery powered systems where the CPU is not running

continuously (Idle mode).

6.16.1 Features

• Measures the passage of time to maintain a calendar and clock.

• Ultra Low Power design to support battery powered systems.

• Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day

of Year.

• Programmable Reference Clock Divider allows adjustment of the RTC to match

various crystal frequencies.

6.17 Pulse width modulator

The PWM is based on the standard Timer block and inherits all of its features, although

only the PWM function is pinned out on the LPC2104/2105/2106. The Timer is designed

to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or

perform other actions when speciﬁed timer values occur, based on seven match registers.

It also includes four capture inputs to save the timer value when an input signal transitions,

and optionally generate an interrupt when those events occur. The PWM function is in

addition to these features, and is based on match register events.

The ability to separately control rising and falling edge locations allows the PWM to be

used for more applications. For instance, multi-phase motor control typically requires three

non-overlapping PWM outputs with individual control of all three pulse widths and

positions.

Two match registers can be used to provide a single edge controlled PWM output. One

match register (MR0) controls the PWM cycle rate, by resetting the count upon match.

The other match register controls the PWM edge position. Additional single edge

controlled PWM outputs require only one match register each, since the repetition rate is

the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a

rising edge at the beginning of each PWM cycle, when an MR0 match occurs.

Three match registers can be used to provide a PWM output with both edges controlled.

Again, the MR0 match register controls the PWM cycle rate. The other match registers

control the two PWM edge positions. Additional double edge controlled PWM outputs

require only two match registers each, since the repetition rate is the same for all PWM

outputs.

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