LPC2124FBD64SLASH00 datasheet(8/40 Pages) NXP

8 / 40 page

LPC2114_2124_6

Product data sheet

Rev. 06 — 10 December 2007

8 of 40

NXP Semiconductors

LPC2114/2124

Single-chip 16/32-bit microcontrollers

P1[16]/

TRACEPKT0

Trace Packet, bit 0. Standard I/O port with internal pull-up.

P1[17]/

TRACEPKT1

Trace Packet, bit 1. Standard I/O port with internal pull-up.

P1[18]/

TRACEPKT2

Trace Packet, bit 2. Standard I/O port with internal pull-up.

P1[19]/

TRACEPKT3

Trace Packet, bit 3. Standard I/O port with internal pull-up.

P1[20]/

TRACESYNC

Trace Synchronization. Standard I/O port with internal pull-up.

Note: LOW on this pin while RESET is LOW, enables pins P1[25:16] to operate as

Trace port after reset.

P1[21]/

PIPESTAT0

Pipeline Status, bit 0. Standard I/O port with internal pull-up.

P1[22]/

PIPESTAT1

Pipeline Status, bit 1. Standard I/O port with internal pull-up.

P1[23]/

PIPESTAT2

Pipeline Status, bit 2. Standard I/O port with internal pull-up.

P1[24]/

TRACECLK

Trace Clock. Standard I/O port with internal pull-up.

P1[25]/EXTIN0

External Trigger Input. Standard I/O with internal pull-up.

P1[26]/RTCK

I/O

Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger

synchronization when processor frequency varies. Bidirectional pin with internal

pull-up.

Note: LOW on this pin while RESET is LOW, enables pins P1[31:26] to operate as

Debug port after reset.

P1[27]/TDO

Test Data out for JTAG interface.

P1[28]/TDI

Test Data in for JTAG interface.

P1[29]/TCK

Test Clock for JTAG interface. This clock must be slower than 1

⁄6 of the CPU clock

(CCLK) for the JTAG interface to operate.

P1[30]/TMS

Test Mode Select for JTAG interface.

P1[31]/TRST

Test Reset for JTAG interface.

n.c.

pin not connected.

RESET

external reset input; a LOW on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor execution to begin at

address 0. TTL with hysteresis, 5 V tolerant.

XTAL1

input to the oscillator circuit and internal clock generator circuits.

XTAL2

output from the oscillator ampliﬁer.

VSS

6, 18, 25,

42, 50

ground: 0 V reference.

VSSA

analog ground; 0 V reference. This should nominally be the same voltage as VSS,

but should be isolated to minimize noise and error.

VSSA(PLL)

PLL analog ground; 0 V reference. This should nominally be the same voltage as

VSS, but should be isolated to minimize noise and error.

VDD(1V8)

17, 49

1.8 V core power supply; this is the power supply voltage for internal circuitry.

Table 3.

Pin description …continued

Symbol

Type Description

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