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LPC2124FBD64/00 数据表(PDF) 11 Page - NXP Semiconductors |
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LPC2124FBD64/00 数据表(HTML) 11 Page - NXP Semiconductors |
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11 / 40 page ![]() LPC2114_2124_6 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 06 — 10 December 2007 11 of 40 NXP Semiconductors LPC2114/2124 Single-chip 16/32-bit microcontrollers However, the ISP flash erase command can be executed at any time (no matter whether the CRP is on or off). Removal of CRP is achieved by erasure of full on-chip user flash. With the CRP off, full access to the chip via the JTAG and/or ISP is restored. 6.3 On-chip static RAM On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8 bit, 16 bit, and 32 bit. The LPC2114/2124 provide 16 kB of static RAM. 6.4 Memory map The LPC2114/2124 memory maps incorporate several distinct regions, as shown in Figure 3. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either flash memory (the default) or on-chip static RAM. This is described in Section 6.17 “System control”. |
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