LPC2124FBD64SLASH00 datasheet(10/40 Pages) NXP

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LPC2114_2124_6

Product data sheet

Rev. 06 — 10 December 2007

10 of 40

NXP Semiconductors

LPC2114/2124

Single-chip 16/32-bit microcontrollers

Functional description

Details of the LPC2114/2124 systems and peripheral functions are described in the

following sections.

6.1 Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on

Reduced Instruction Set Computer (RISC) principles, and the instruction set and related

decode mechanism are much simpler than those of microprogrammed Complex

Instruction Set Computers. This simplicity results in a high instruction throughput and

impressive real-time interrupt response from a small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems

can operate continuously. Typically, while one instruction is being executed, its successor

is being decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as

Thumb, which makes it ideally suited to high-volume applications with memory

restrictions, or applications where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

• The standard 32-bit ARM set.

• A 16-bit Thumb set.

The Thumb set’s 16-bit instruction length allows it to approach twice the density of

standard ARM code while retaining most of the ARM’s performance advantage over a

traditional 16-bit processor using 16-bit registers. This is possible because Thumb code

operates on the same 32-bit register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

6.2 On-chip ﬂash program memory

The LPC2114/2124 incorporate a 128 kB and 256 kB ﬂash memory system respectively.

This memory may be used for both code and data storage. Programming of the ﬂash

memory may be accomplished in several ways. It may be programmed In System via the

serial port. The application program may also erase and/or program the ﬂash while the

application is running, allowing a great degree of ﬂexibility for data storage ﬁeld ﬁrmware

upgrades, etc. When on-chip bootloader is used, 120 kB and 248 kB of ﬂash memory is

available for user code.

The LPC2114/2124 ﬂash memory provides a minimum of 100000 erase/write cycles and

20 years of data retention.

On-chip bootloader (as of revision 1.60) provides Code Read Protection (CRP) for the

LPC2114/2124 on-chip ﬂash memory. When the CRP is enabled, the JTAG debug port

and ISP commands accessing either the on-chip RAM or ﬂash memory are disabled.

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