SC102205 datasheet(64/140 Pages) FREESCALE

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Device User Guide — 9S12DT128DGV2/D V02.17

Freescale Semiconductor

2.3 Detailed Signal Descriptions

2.3.1 EXTAL, XTAL — Oscillator Pins

EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived

from the EXTAL input frequency. XTAL is the crystal output.

2.3.2 RESET — External Reset Pin

An active low bidirectional control signal, it acts as an input to initialize the MCU to a known start-up

state, and an output when an internal MCU function causes a reset.

2.3.3 TEST — Test Pin

This input only pin is reserved for test.

NOTE:

The TEST pin must be tied to VSS in all applications.

2.3.4 XFC — PLL Loop Filter Pin

PLL loop filter. Please ask your Freescale representative for the interactive application note to compute

PLL loop filter elements. Any current leakage on this pin must be avoided.

Figure 2-4 PLL Loop Filter Connections

2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin

The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug

communication. In MCU expanded modes of operation when instruction tagging is on, an input low on

this pin during the falling edge of E-clock tags the high half of the instruction word being read into the

instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is

latched to the MODC bit at the rising edge of RESET. This pin has a permanently enabled pull-up device.

MCU

XFC

VDDPLL

SC102205 数据表(PDF) 64 Page - Freescale Semiconductor, Inc