P89LPC9331FDH datasheet(2/93 Pages) NXP

2 / 93 page

P89LPC9331_9341_9351_9361_3

Product data sheet

Rev. 03 — 2 June 2009

2 of 93

NXP Semiconductors

P89LPC9331/9341/9351/9361

8-bit microcontroller with accelerated two-clock 80C51 core

2.2 Additional features

I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns

for all instructions except multiply and divide when executing at 18 MHz. This is six

times the performance of the standard 80C51 running at the same clock frequency. A

lower clock frequency for the same performance results in power savings and reduced

EMI.

I Serial ﬂash In-Circuit Programming (ICP) allows simple production coding with

commercial EPROM programmers. Flash security bits prevent reading of sensitive

application programs.

I Serial ﬂash In-System Programming (ISP) allows coding while the device is mounted

in the end application.

I In-Application Programming (IAP) of the ﬂash code memory. This allows changing the

code in a running application.

I Watchdog timer with separate on-chip oscillator, nominal 400 kHz, calibrated to ±5%,

requiring no external components. The watchdog prescaler is selectable from

eight values.

I High-accuracy internal RC oscillator option, with clock doubler option, allows operation

without external oscillator components. The RC oscillator option is selectable and ﬁne

tunable.

I Clock switching on the ﬂy among internal RC oscillator, watchdog oscillator, external

clock source provides optimal support of minimal power active mode with fast

switching to maximum performance.

I Idle and two different power-down reduced power modes. Improved wake-up from

Power-down mode (a LOW interrupt input starts execution). Typical power-down

current is 1

µA (total power-down with voltage comparators disabled).

I Active-LOW reset. On-chip power-on reset allows operation without external reset

components. A software reset function is also available.

I Conﬁgurable on-chip oscillator with frequency range options selected by user

programmed ﬂash conﬁguration bits. Oscillator options support frequencies from

20 kHz to the maximum operating frequency of 18 MHz.

I Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator

allowing it to perform an oscillator fail detect function.

I Programmable port output conﬁguration options: quasi-bidirectional, open drain,

push-pull, input-only.

I High current sourcing/sinking (20 mA) on eight I/O pins (P0.3 to P0.7, P1.4, P1.6,

P1.7). All other port pins have high sinking capability (20 mA). A maximum limit is

speciﬁed for the entire chip.

I Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of

the pins match or do not match a programmable pattern.

I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns

minimum ramp times.

I Only power and ground connections are required to operate the

P89LPC9331/9341/9351/9361 when internal reset option is selected.

I Four interrupt priority levels.

I Eight keypad interrupt inputs, plus two additional external interrupt inputs.

I Schmitt trigger port inputs.

I Second data pointer.

I Emulation support.

P89LPC9331FDH 数据表(PDF) 2 Page - NXP Semiconductors

P89LPC9331FDH 数据表(HTML) 2 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93

数据表下载