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MC9S08JS16CFK 数据表(PDF) 22 Page - Freescale Semiconductor, Inc |
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MC9S08JS16CFK 数据表(HTML) 22 Page - Freescale Semiconductor, Inc |
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22 / 32 page ![]() MC9S08JS16 Series MCU Data Sheet, Rev. 4 Electrical Characteristics Freescale Semiconductor 22 Table 11. SPI Electrical Characteristic Num1 1 Refer to Figure 18 through Figure 21. C Characteristic2 2 All timing is shown with respect to 20% V DD and 80% VDD, unless noted; 50 pF load on all SPI pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output pins. Symbol Min Typical Max Unit 1D Operating frequency3 Master Slave 3 The maximum frequency is 8 MHz when input filter on SPI pins is disabled. fop fop fBus/2048DC — — fBus/2 fBus/4 Hz 2D Cycle time Master Slave tSCK tSCK 2 4 — — 2048 — tcyc 3D Enable lead time Master Slave tLead tLead — — 1/2 1/2 — — tSCK 4D Enable lag time Master Slave tLag tLag — — 1/2 1/2 — — tSCK 5D Clock (SPSCK) high time Master Slave tSCKH — 1/2 tSCK – 25 1/2 tSCK 1/2 tSCK — — ns 6D Clock (SPSCK) low time Master Slave tSCKL — 1/2 tSCK – 25 1/2 tSCK 1/2 tSCK — — ns 7D Data setup time (inputs) Master Slave tSI(M) tSI(S) 30 30 — — — — ns 8D Data hold time (inputs) Master Slave tHI(M) tHI(S) 30 30 — — — — ns 9 D Access time, slave4 4 Time to data active from high-impedance state. tA —— 40 ns 10 D Disable time, slave5 5 Hold time to high-impedance state. tdis —— 40 ns 11 D Data setup time (outputs) Master Slave tSO tSO — — — — 25 25 ns 12 D Data hold time (outputs) Master Slave tHO tHO –10 –10 — — — — ns |
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