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PCA9600DP 数据表(PDF) 5 Page - NXP Semiconductors |
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PCA9600DP 数据表(HTML) 5 Page - NXP Semiconductors |
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5 / 30 page ![]() PCA9600_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 11 November 2009 5 of 30 NXP Semiconductors PCA9600 Dual bidirectional bus buffer Remark: Two or more SX or SY I/Os must not be interconnected. The PCA9600 design does not support this configuration. Bidirectional I2C-bus signals do not allow any direction control pin so, instead, slightly different logic LOW voltage levels are used at SX/SY to avoid latching of this buffer. A ‘regular I2C-bus LOW’ applied at the RX/RY of a PCA9600 will be propagated to SX/SY as a ‘buffered LOW’ with a slightly higher voltage level. If this special ‘buffered LOW’ is applied to the SX/SY of another PCA9600, that second PCA9600 will not recognize it as a ‘regular I2C-bus LOW’ and will not propagate it to its TX/TY output. The SX/SY side of PCA9600 may not be connected to similar buffers that rely on special logic thresholds for their operation, for example P82B96, PCA9511A, PCA9515A, ‘B’ side of PCA9517, etc. The SX/SY side is only intended for, and compatible with, the normal I2C-bus logic voltage levels of I2C-bus master and slave chips, or even TX/RX signals of a second PCA9600 or P82B96 if required. The TX/RX and TY/RY I/O pins use the standard I2C-bus logic voltage levels of all I2C-bus parts. There are no restrictions on the interconnection of the TX/RX and TY/RY I/O pins to other PCA9600s, for example in a star or multipoint configuration with the TX/RX and TY/RY I/O pins on the common bus and the SX/SY side connected to the line card slave devices. For more details see Application Note AN10658, “Sending I2C-bus signals via long communication cables”. The PCA9600 is a direct upgrade of the P82B96 with the significant differences summarized in Table 4. Table 4. PCA9600 versus P82B96 Detail PCA9600 P82B96 Supply voltage (VCC) range: 2.5 V to 15 V 2 V to 15 V Maximum operating bus voltage (independent of VCC): 15 V 15 V Typical operating supply current: 5 mA 1 mA Typical LOW-level input voltage on I2C-bus (SX/SY side): 0.5 V over −40 °C to +85 °C 0.65 V at 25 °C LOW-level output voltage on I2C-bus (SX/SY side; 3 mA sink): 0.74 V (max.) over −40 °C to +85 °C 0.88 V (typ.) at 25 °C LOW-level output voltage on Fm+ I2C-bus (SX/SY side; 7 mA sink): 1 V (max.) n/a Temperature coefficient of VIL /VOL: 0 mV/ °C −2 mV/°C Logic voltage levels on SX/SY bus (independent of VCC): compatible with I2C-bus and similar buses using TTL levels (SMBus, etc.) compatible with I2C-bus and similar buses using TTL levels (SMBus, etc.) Typical propagation delays: < 100 ns < 200 ns TX/RX switching specifications (I2C-bus compliant): yes, all classes including 1 MHz Fm+ yes, all classes including Fm+ RX logic levels with tighter control than I2C-bus limit of 30 % to 70 %: yes, 40 % to 55 % (48 % nominal) yes, 42 % to 58 % (50 % nominal) Maximum bus speed: > 1 MHz > 400 kHz ESD rating HBM per JESD22-A114: > 4500 V > 3500 V Package: SO8, TSSOP8 (MSOP8) DIP8, SO8, TSSOP8 (MSOP8) |
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