PCA9600DP datasheet(9/30 Pages) NXP

9 / 30 page

PCA9600_4

Product data sheet

Rev. 04 — 11 November 2009

9 of 30

NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

[1]

The maximum static sink current for a standard I2C-bus is 3 mA and PCA9600 is guaranteed to sink 3 mA at SX/SY when those pins are

holding the bus LOW. However, when an external device pulls the SX/SY pins below 1.4 V, the PCA9600 may source a current between

0 mA and 1 mA maximum. During contention an external device is required to pull the bus connected to SX or SY down to the 0.4 V

level referenced in the I2C-bus speciﬁcation. So that device must be able to sink up to 1 mA from SX/SY plus the usual pull-up current.

Therefore the external pull-up used at SX/SY should be limited to 2 mA. The typical and maximum currents sourced by SX/SY as a

function of junction temperature are shown in Figure 10, and the equivalent circuit at the SX/SY interface is shown in Figure 4.

[2]

Valid over temperature for VCC ≤ 5 V. At higher VCC, this current may increase to maximum −20 µA at VCC =15V.

[3]

The input logic threshold is independent of the supply voltage.

[4]

The minimum value requirement for pull-up current, 0.3 mA, guarantees that the minimum value for VSX output LOW will always exceed

the maximum VSX input HIGH level to eliminate any possibility of latching. The speciﬁed difference is guaranteed by design within any

IC. While the tolerances on absolute levels allow a small probability, the LOW from one SX output is recognized by an SX input of

another PCA9600, this has no consequences for normal applications. In any design the SX pins of different ICs should never be linked

because the resulting system would be very susceptible to induced noise and would not support all I2C-bus operating modes.

[5]

The fall time of VTX from 5 V to 2.5 V in the test is approximately 10 ns.

The fall time of VSX from 5 V to 2.5 V in the test is approximately 20 ns.

The rise time of VTX from 0 V to 2.5 V in the test is approximately 15 ns.

The rise time of VSX from 0.7 V to 2.5 V in the test is approximately 25 ns.

Buffer response time[5]

VCC = 5 V; pin TX pull-up resistor = 160 Ω; pin SX pull-up resistor = 2.2 kΩ; no capacitive load

delay time

VSX to VTX, VSY to VTY; on

falling input between

VSX = input switching

threshold, and VTX output

falling to 50 % VCC

-50

VSX to VTX, VSY to VTY; on

rising input between

VSX = input switching

threshold, and VTX output

reaching 50 % VCC

-60

VRX to VSX, VRY to VSY; on

falling input between

VRX = input switching

threshold, and VSX output

falling to 50 % VCC

100

VRX to VSX, VRY to VSY; on

rising input between

VRX = input switching

threshold, and VSX output

reaching 50 % VCC

-95

Input capacitance

input capacitance

effective input capacitance of

any signal pin measured by

incremental bus rise times;

guaranteed by design, not

production tested

--10

Table 6.

Characteristics …continued

Tamb = −40 °C to +85 °C unless otherwise speciﬁed; voltages are speciﬁed with respect to GND with VCC = 2.5 V to 15 V

unless otherwise speciﬁed. Typical values are measured at VCC = 5 V and Tamb =25 °C.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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