PCA9600_4

© NXP B.V. 2009. All rights reserved.

Product data sheet

Rev. 04 — 11 November 2009

14 of 30

NXP Semiconductors

PCA9600

Dual bidirectional bus buffer

10.1 Calculating system delays and bus clock frequency

C = F; V = V.

Fig 15. Falling edge of SCL at master is delayed by the buffers and bus fall times

PCA9600

PCA9600

SCL

SX

local master bus

SCL

MASTER

Cs

slave bus

capacitance

Cb

buffered bus

wiring capacitance

Cm

master bus

capacitance

Rm

GND (0 V)

buffered expansion bus

TX/RX

TX/RX

SX

Rb

Rs

SLAVE

remote slave bus

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Effective delay of SCL at master: 115 + (Rm

× Cm) + (0.7 × Rb × Cb) (ns).

C = F; R =

Ω.

Fig 16. Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times

PCA9600

SX

local master bus

SCL

MASTER

Cb

buffered bus

wiring capacitance

Cm

master bus

capacitance

Rm

GND (0 V)

buffered expansion bus

TX/RX

TX/RX

Rb

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