LTC4360-1/LTC4360-2

7

436012f

APPLICATIONS INFORMATION

a similar rate which results in an inrush current into the

dt

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The servo loop is compensated by the parasitic capaci-

tance of the external MOSFET. No further compensation

components are normally required. In the case where

the parasitic capacitance is less than 100pF, a 100pF

compensation capacitor between GATE and ground may

be required.

An even slower GATE ramp and lower inrush current

from GATE to ground. The voltage at GATE then ramps

the formula:

10µA

Overvoltage

30mA fast pull-down on GATE within 1μs. After an over-

again remains below 5.7V for 130ms.

PWRGD Output

PWRGD is an active low output with a MOSFET pull-

down to ground and a 500k resistive pull-up to OUT. The

PWRGD pin pull-down releases during the low current

sleep mode (invoked by ON high), UVLO or overvolt-

age and the subsequent 130ms start-up delay. After the

start-up delay, GATE starts its slow ramp-up and control

of the PWRGD pull-down passes on to the GATE high

the pull-down. The PWRGD pull-down is capable of sink-

ing up to 3mA of current allowing it to drive an optional

LED. To interface PWRGD to another I/O rail, connect a

resistor from PWRGD to the I/O rail with a resistance

low enough to override the internal 500k pull-up to OUT.

Figure 2 details PWRGD behavior for a LTC4360-1 with

1k pull-up to 5V at PWRGD.

ON Input (LTC4360-1)

ON is a CMOS compatible, active low enable input. It has

a default 5μA pull-down to ground. Connect this pin to

ground or leave open to enable normal device operation.

If it is driven high while the external MOSFET is turned on,

GATE is pulled low with a weak pull-down current (40μA)

to turn off the external MOSFET gradually, minimizing input

voltage transients. The LTC4360-1 then goes into a low cur-

rent sleep mode, drawing only 1.5μA at IN. When ON goes

back low, the part restarts with a 130ms delay cycle.

GATEP Control (LTC4360-2)

GATEP has a 2M resistive pull-down to ground and a 5.8V

Zener clamp in series with a 200k resistor to IN. It con-

trols the gate of an optional external P-channel MOSFET

to provide negative voltage protection. The 2M resistive

more than the MOSFET gate threshold voltage. The IN to

GATEP Zener protects the MOSFET from gate overvoltage

Figure 2. PWRGD Behavior

IN

OUT

GATE

ON

PWRGD

START-UP

FROM UVLO

RESTART

FROM OV

OV

RESTART

FROM ON

ON

130ms

65ms

130ms

65ms

130ms

65ms