 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
HT66F40 数据表(PDF) 89 Page - Holtek Semiconductor Inc |
|
|
|||||||||||||||||||||||||||||
HT66F40 数据表(HTML) 89 Page - Holtek Semiconductor Inc |
|
|
89 / 250 page  HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Rev. 1.20 89 June 4, 2010 · TM0AH Register Bit 76543210 Name ¾¾¾¾¾¾ D9 D8 R/W ¾¾¾¾¾¾ R/W R/W POR ¾¾¾¾¾¾ 00 Bit 7~2 Unimplemented, read as ²0² Bit 1~0 TM0AH: TM0 CCRA High Byte Register bit 1 ~ bit 0 TM0 10-bit CCRA bit 9 ~ bit 8 · TM0C0 Register Bit 76543210 Name T0PAU T0CK2 T0CK1 T0CK0 T0ON T0RP2 T0RP1 T0RP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 00000000 Bit 7 T0PAU: TM0 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4 T0CK2~T0CK0: Select TM0 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Reserved 110: TCK0 rising edge clock 111: TCK0 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3 T0ON: TM0 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T0OC bit, when the T0ON bit changes from low to high. Bit 2~0 T0RP2~T0RP0: TM0 CCRP 3-bit register, compared with the TM0 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM0 clocks 001: 128 TM0 clocks 010: 256 TM0 clocks 011: 384 TM0 clocks 100: 512 TM0 clocks 101: 640 TM0 clocks 110: 768 TM0 clocks 111: 896 TM0 clocks |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
