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LTC694CS8PBF 数据表(PDF) 12 Page - Linear Technology

部件名 LTC694CS8PBF
功能描述  Microprocessor Supervisory Circuits
PDF  18 Pages
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC694CS8PBF 数据表(HTML) 12 Page - Linear Technology

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LTC690/LTC691
LTC694/LTC695
12
690fe
Power-Fail Warning
The LTC690 family generates a Power Failure Output
(PFO) for early warning of failure in the microprocessor’s
power supply. This is accomplished by comparing the
Power Failure Input (PFI) with an internal 1.3V reference.
PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 5V output. The voltage
divider ratio can be chosen such that the voltage at the PFI
pin falls below 1.3V several milliseconds before the 5V
supply falls below the maximum reset voltage threshold
4.75V. PFO is normally used to interrupt the microprocessor
to execute shutdown procedure between PFO and RESET
or RESET.
The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resistor
between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the summing
junction at the PFI pin.
V = 1.3V 1+
R1
R2
R1
R3
H
+
When PFO output is high, the series combination of R3
and R4 source current into the PFI summing junction.
V
1.3V 1
R1
R2
(5V – 1.3V)R1
1.3V(R3 R4)
L =+
+
Assuming R4
R3,V
5V
R1
R3
HYSTERESIS
<<
=
Example 1: The circuit in Figure 8 demonstrates the use
of the power-fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of the
supply input VINis100mV/msandthetotaltimetoexecutea
shutdown procedure is 8ms. Also the noise of VINis200mV.
With these assumptions in mind, we can reasonably set
VL = 7.5V which 1.25V greater than the sum of maximum
reset voltage threshold and the dropout voltageof LT1086-5
(4.75V + 1.5V) and VHYSTERESIS = 850mV.
APPLICATIONS INFORMATION
Figure 6. A Typical Nonvolatile CMOS RAM Application
5V
3V
0.1μF
10μF
VBATT
VCC
LTC691
LTC695
VOUT
GND
690 F06
VCC
RESET
CE IN
CE OUT
RESET
0.1μF
TO μP
FROM DECODER
CS
20ns PROPAGATION DELAY
62512
RAM
GND
+
5V
3V
0.1μF
10μF
VBATT
VCC
LTC690
LTC694
VOUT
GND
690 F07
VCC
RESET
0.1μF
CS
62128
RAM
CS1
CS2
GND
+
10μF
100μF
VIN
VOUT
ADJ
690 F08
VCC
0.1μF
TO μP
PFO
GND
LT1086-5
VIN ≥ 7.5V
R4
10k
PFI
LTC690/LTC691
LTC694/LTC695
R1
51k
R2
10k
R3
300k
5V
+
+
10μF
10μF
VIN VOUT
ADJ
1690 F09
0.1μF
TO μP
LT1086-5
VIN ≥ 6.5V
R4
10k
R1
27k
R3
2.7M
R2
8.2k
5V
R5
3.3k
VCC
GND
PFO
PFI
LTC690/LTC691
LTC694/LTC695
+
+
Figure 7. Write Protect for RAM with LTC690 or LTC694
Figure 8. Monitoring Unregulated DC Supply
with the LTC690’s Power-Fail Comparator
Figure 9. Monitoring Regulated DC Supply
with the LTC690’s Power-Fail Comparator



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