LTC690/LTC691

LTC694/LTC695

13

690fe

APPLICATIONS INFORMATION

V5V

R1

R3

850V

R3 ≈ 5.88 R1

Choose R3 = 300k and R1 = 51k. Also select R4 = 10k

which is much smaller than R3.

7.5V = 1.3V 1+

R2

–

(5V – 1.3V)51

51

1 3 310

kk

Vk

.(

)

⎛

⎝

⎜

⎞

⎠

⎟

R2 = 9.7kΩ, Choose nearest 5% resistor 10k and recalcu-

V1.3V 1

10k

–

(5V – 1.3V)51

1.3V(310k

⎛

⎝

⎜

⎞

⎠

⎟ =

51

732

kk

)

.V

V1.3V 1

51k

10k

51k

300k

8.151V

+

⎛

⎝

⎜

⎞

⎠

⎟ =

(7.32V – 6.25V)

100mV/ms

10.7ms

=

The 10.7ms allows enough time to execute shutdown

procedure for microprocessor and 831mV of hysteresis

Example 2: The circuit in Figure 9 can be used to measure

the regulated 5V supply to provide early warning of power

failure. Because of variations in the PFI threshold, this

circuit requires adjustment to ensure the PFI comparator

trips before the reset threshold is reached. Adjust R5 such

the desired level (e.g., 4.85V).

Monitoring the Status of the Battery

C3 can also monitor the status of the memory back-up

battery (Figure 10). If desired, the CE OUT can be used to

apply a test load to the battery. Since CE OUT is forced high

in battery back-up mode, the test load will not be applied

to the battery while it is in use, even if the microprocessor

is not powered.

3V

5V

690 F10

R1

1M

20k

R2

1M

OPTIONAL TEST LOAD

LOW-BATTERY SIGNAL

TO μP I/O PIN

I/O PIN

GND

PFI

LTC691

LTC695

CE IN

PFO

CE OUT

Figure 10. Back-Up Battery Monitor with Optional Test Load

Watchdog Timer

The LTC690 family provides a watchdog timer function

to monitor the activity of the microprocessor. If the

microprocessor does not toggle the Watchdog Input

(WDI) within a seleced timeout period, RESET is forced to

active low for a minimum of 35ms for the LTC690/LTC691

(140ms for the LTC694/LTC695). The reset active time is

adjustable on the LTC691/LTC695. Since many systems

can not service the watchdog timer immediately after

a reset, the LTC691 and LTC695 have longer timeout

period (1.0 second minimum) right after a reset is issued.

The normal timeout period (70ms minimum) becomes

effective following the first transition of WDI after RESET

is inactive. The watchdog timeout period is fixed at 1.0

second minimum on the LTC690 and LTC694. Figure 11

shows the timing diagram of watchdog timeout period and

reset active time. The watchdog timeout period is restarted

as soon as RESET is inactive. When either a high-to-low

or low-to-high transition occurs at the WDI pin prior to

timeout, the watchdog time is reset and begins to time

out again. To ensure the watchdog time does not time

out, either a high-to-low or low-to-high transition on the

WDI pin must occur at or less than the minimum timeout

period. If the input to the WDI pin remains either high or

low, reset pulses will be issued every 1.6 seconds typically.

The watchdog time can be deactivated by floating the WDI