LTC690/LTC691

LTC694/LTC695

5

690fe

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND.

Note 3: For military temperature range parts or for the LTC692 and

LTC693, consult the factory.

Note 4: The output pins of BATT ON, LOW⎯LINE, PFO, WDO, RESET and

RESET have weak internal pull-ups of typically 3μA. However, external pull-

up resistors may be used when higher speed is required.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

RESET, RESET, WDO, LOW⎯LINE

Output Short-Circuit Current (Note 4)

Output Source Current

1

3

25

μA

Output Sink Current

25

mA

WDI Input Threshold

Logic Low

Logic high

3.5

0.8

V

WDI Input Current

WDI = 0V

l

l

–50

4

–8

50

μA

Power-Fail Detector

PFI Input Threshold

l

1.25

1.3

1.35

V

PFI Input Threshold PSRR

0.3

mV/V

PFI Input Current

±0.01

±25

nA

PFO Output Voltage (Note 4)

3.5

0.4

V

PFO Short-Circuit Source Current (Note 4)

PFI = HIGH, PFO = 0V

1

3

25

μA

25

mA

PFI Comparator Response Time (Falling)

2

μs

PFI Comparator Response Time (Rising) (Note 4)

with 10kΩ Pull-Up

40

8

μs

Chip Enable Gating

CE IN Threshold

2

0.8

V

CE IN Pull-Up Current (Note 7)

3μA

CE OUT Output Voltage

0.4

V

CE Propagation Delay

l

20

20

35

45

ns

CE OUT Output Short-Circuit Current

Output Source Current

Output Sink Current

30

35

mA

Oscillator

OSC IN Input Current (Note 7)

±2

μA

OSC SEL Input Pull-Up Current (Note 7)

5μA

OSC IN Frequency Range

OSC SEL = 0V

l

0

250

kHz

OSC IN Frequency with External Capacitor

4

kHz

Note 5: The LTC690 and LTC691 have minimum reset active time of 35ms

(50ms typically) while the LTC694 and LTC695 have longer minimum

reset active time of 140ms (200ms typically). The reset active time of

the LTC691 and LTC695 can be adjusted (see Table 2 in Applications

Information section).

Note 6: The external clock feeding into the circuit passes through the

oscillator before clocking the watchdog timer (See Block Diagram).

Variation in the timeout period is caused by phase errors which occur

when the oscillator divides the external clock by 64. The resulting variation

in the timeout period is 64 clocks plus one clock of jitter.

Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal

pullups which pull to the supply when the input pins are floating.