LTC2453

7

2453fb

CONVERTER OPERATION

Converter Operation Cycle

The LTC2453 is a low-power, fully differential, delta-sigma

ation, as shown in Figure 1, is composed of three successive

states: CONVERSION, SLEEP and DATA OUTPUT.

Initially, at power up, the LTC2453 performs a conversion.

Once the conversion is complete, the device enters the

sleep state. While in this sleep state, power consumption is

reduced by several orders of magnitude. The part remains

in the sleep state as long as it is not addressed for a read

operation. The conversion result is held indefinitely in a

static shift register while the part is in the sleep state.

APPLICATIONS INFORMATION

edges of SCL, allowing the user to reliably latch data on

the rising edge of SCL. A new conversion is initiated by

a stop condition following a valid read operation, or by

the conclusion of a complete read cycle (all 16 bits read

out of the device).

Power-Up Sequence

verter is below approximately 2.1V, the ADC performs a

power-on reset. This feature guarantees the integrity of

the conversion result.

generates an internal power-on reset (POR) signal for

approximately 0.5ms. The POR signal clears all internal

registers. Following the POR signal, the LTC2453 starts

a conversion cycle and follows the succession of states

described in Figure 1. The first conversion result fol-

lowing POR is accurate within the specifications of the

the operating range (2.7V to 5.5V) before the end of the

POR time interval.

Ease of Use

The LTC2453 data output has no latency, filter settling delay

or redundant results associated with the conversion cycle.

There is a one-to-one correspondence between the conver-

sion and the output data. Therefore, multiplexing multiple

analog input voltages requires no special actions.

The LTC2453 performs offset calibrations every conver-

sion. This calibration is transparent to the user and has

no effect upon the cyclic operation described previ-

ously. The advantage of continuous calibration is extreme

stability of the ADC performance with respect to time and

temperature.

The LTC2453 includes a proprietary input sampling scheme

that reduces the average input current by several orders

of magnitude when compared to traditional delta-sigma

architectures. This allows external filter networks to

interface directly to the LTC2453. Since the average input

sampling current is 50nA, an external RC lowpass filter

using a 1k

Ω and 0.1μF results in <1LSB additional error.

Additionally, there is negligible leakage current between

READ

ACKNOWLEDGE

DATA OUTPUT

YES

YES

2453 F01

STOP

OR READ

16-BITS

SLEEP

CONVERSION

POWER-ON RESET

NO

NO

Figure 1. LTC2453 State Diagram

The device will not acknowledge an external request during

the conversion state. After a conversion is finished, the

device is ready to accept a read request. The LTC2453’s

address is hard-wired at 0010100. Once the LTC2453 is

addressed for a read operation, the device begins output-

ting the conversion result under the control of the serial

clock (SCL). There is no latency in the conversion result.

The data output is 16 bits long and contains a 15-bit plus

sign conversion result. Data is updated on the falling