LTC2453_1 datasheet(8/18 Pages) LINER

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LTC2453

2453fb

Reference Voltage Range

This converter accepts a truly differential external reference

voltage. The absolute/common mode voltage range for

REF+ and REF– pins covers the entire operating range of

the device (GND to VCC). For correct converter operation,

VREF+ must be >(2.5V + VREF–).

The LTC2453 differential reference input range is 2.5V to

VCC. For the simplest operation, REF+ can be shorted to

VCC and REF– can be shorted to GND.

Input Voltage Range

For most applications, VREF– ≤ (VIN+, VIN–) ≤ VREF+. Under

these conditions the output code is given (see Data Format

section) as 32768 • (VIN+ – VIN–)/(VREF+ – VREF–) + 32768.

The output of the LTC2453 is clamped at a minimum value

of 0 and clamped at a maximum value of 65535.

The LTC2453 includes a proprietary system that can,

typically, correctly digitize each input 8LSB above

VREF+ and below VREF–, if the LTC2453’s output is not

clamped. As an example (Figure 2), if the user desires to

measure a signal slightly below ground, the user could

set VIN– = VREF– = GND, and VREF+ = 5V. If VIN+ = GND,

the output code would be approximately 32768. If VIN+

= GND – 8LSB = –1.22 mV, the output code would be

approximately 32760.

I2C INTERFACE

The LTC2453 communicates through an I2C interface. The

I2C interface is a 2-wire open-drain interface supporting

multiple devices and masters on a single bus. The

connected devices can only pull the data line (SDA) LOW

and never drive it HIGH. SDA must be externally connected

to the supply through a pull-up resistor. When the data line

is free, it is HIGH. Data on the I2C bus can be transferred

at rates up to 100kbits/s in the Standard-Mode and up to

400kbits/s in the Fast-Mode. The VCC power should not

be removed from the device when the I2C bus is active to

avoid loading the I2C bus lines through the internal ESD

protection diodes.

Each device on the I2C bus is recognized by a unique

address stored in that device and can operate either as

a transmitter or receiver, depending on the function of

the device. In addition to transmitters and receivers,

devices can also be considered as masters or slaves when

performing data transfers. A master is the device which

initiates a data transfer on the bus and generates the

clock signals to permit that transfer. Devices addressed

by the master are considered a slave. The address of the

LTC2453 is 0010100.

The LTC2453 can only be addressed as a slave. It can only

transmit the last conversion result. The serial clock line,

SCL, is always an input to the LTC2453 and the serial data

line SDA is bidirectional. Figure 3 shows the deﬁnition of

the I2C timing.

The START and STOP Conditions

A START (S) condition is generated by transitioning SDA

from HIGH to LOW while SCL is HIGH. The bus is considered

to be busy after the START condition. When the data

transfer is ﬁnished, a STOP (P) condition is generated by

transitioning SDA from LOW to HIGH while SCL is HIGH.

The bus is free after a STOP is generated. START and STOP

conditions are always generated by the master.

When the bus is in use, it stays busy if a repeated START

(Sr) is generated instead of a STOP condition. The repeated

START timing is functionally identical to the START and

is used for reading from the device before the initiation

of a new conversion.

VIN

+/VREF+

–0.001

32772

32780

32788

0.001

2453 F02

32764

32756

32768

32776

32784

32760

32752

32748

–0.005

0.005

0.0015

SIGNALS

BELOW

GND

Figure 2. Output Code vs VIN+ with VIN– = 0 and VREF– = 0

APPLICATIONS INFORMATION

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