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STE100P

5

HARDWARE CONTROL INTERFACE

5.1

Operating Configurations

The Hardware Control Interface consists of the MF<4:0>, CFG <1:0> and FDE input pins as well as the

LED/PAD pins. This interface is used to configure operating characteristics of the STE100P. The Hard-

ware Control Interface provides initial values for the MDIO registers, and then passes control to the MDIO

Interface. Individual chip addressing via the LED/PAD pins allows multiple STE100P devices to share the

MII interface. Table 3 shows how to set up the desired operating configurations using the Hardware Con-

trol Interface.

Table 3. Operating Configurations / Auto-Negotiation Enabled

Note:

If pin 5, MF0 = 0, or ANE (pin MF0 / PR0:12) = 0 (Auto-Negotiation disabled), then PR4 bits 5-8 will contain the default value indicated

in the table describing register PR4.

5.2

LED / PHY Address Interface

The LED output pins can be used to drive LED’s directly, or can be used to provide status information to

a network management device. The active state of each LED output driver is dependent on the logic level

sampled by the corresponding PHY address input upon power-up/reset. For example, if a given PAD input

is resistively pulled low then the corresponding LED output will be configured as an active high driver. Con-

versely, if a given PAD input is resistively pulled high then the corresponding LED output will be configured

as an active low driver. These outputs are standard CMOS drivers and not open-drain.

The STE100P PAD[4:0] inputs provide up to 32 unique PHY address options. An address selection of all

zeros (00000) will result in a PHY isolation condition as a result of power-on/reset, as documented for PR0

bit 10.

(See Section 7 for more detailed descriptions of device operation.)

Desired

Configuration

Input Value

PR4 Register Bits Affected

CFG0

CFG1

FDE

[8] TXF

[7] TXH

[6] 10F

[5] 10H

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