M24C16, M24C08, M24C04, M24C02, M24C01

DC and AC parameters

Doc ID 5067 Rev 16

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Table 15.

M24Cxx-F)

Test conditions specified in either Table 6, Table 7 or Table 8 and Table 13

Symbol

Alt.

Parameter

1.

Max.(1)

Unit

Clock frequency

400

kHz

Clock pulse width high

600

ns

Clock pulse width low

1300

ns

(2)

2.

Characterized only, not tested in production.

SDA (out) fall time

3.

120

ns

Input signal rise time

(4)

4.

There is no min. or max. values for the input signal rise and fall times. It is however recommended by the

I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when

(4)

ns

Input signal fall time

(4)

(4)

ns

100

ns

0

ns

Data out hold time

100

ns

(5)(6)

5.

To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or

rising edge of SDA.

6.

Clock low to next data valid (access time)

200

900

ns

600

ns

600

ns

600

ns

Time between Stop condition and next Start

condition

1300

ns

Write time

5

ms