P912XDP512F0MPVR datasheet(784/1348 Pages) FREESCALE

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Chapter 20 S12X Debug (S12XDBGV3) Module

MC9S12XDP512 Data Sheet, Rev. 2.21

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Freescale Semiconductor

BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via

a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the S12XCPU actually

executes the BDM ﬁrmware code. It checks the ENABLE and returns if ENABLE is not set. If not serviced

by the monitor then the breakpoint is re-asserted when the BDM returns to normal S12XCPU ﬂow.

If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code

and DBG breakpoint could occur simultaneously. The S12XCPU ensures that BDM requests have a higher

priority than SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid re

triggering a breakpoint.

NOTE

When program control returns from a tagged breakpoint using an RTI or

BDM GO command without program counter modiﬁcation it will return to

the instruction whose tag generated the breakpoint. To avoid re triggering a

breakpoint at the same location reconﬁgure the S12XDBG module in the

SWI routine, if conﬁgured for an SWI breakpoint, or over the BDM

interface by executing a TRACE command before the GO to increment the

program ﬂow past the tagged instruction.

An XGATE software breakpoint is forced immediately, the tracing session

terminated and the XGATE module execution stops. The user can thus

determine if an XGATE breakpoint has occurred by reading out the XGATE

program counter over the BDM interface.

Table 20-45. Breakpoint Mapping Summary

DBGBRK[1]

(DBGC1[3])

BDM Bit

(DBGC1[4])

BDM

Enabled

BDM

Active

S12X Breakpoint

Mapping

No Breakpoint

Breakpoint to SWI

No Breakpoint

Breakpoint to SWI

Breakpoint to BDM

No Breakpoint

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