STM6510 datasheet(9/26 Pages) STMICROELECTRONICS

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STM6510

Description

Doc ID 16788 Rev 2

9/26

1.3

Pin descriptions

1.3.1

Power supply (VCC)

This pin is used to provide the power to the Smart Reset™ device and to monitor the power

supply. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between

the VCC and VSS pins.

1.3.2

Ground (VSS)

This is the supply ground for the device.

1.3.3

Smart Reset™ push-button inputs (SR0, SR1)

Both SR0 and SR1 need to be held active at the same time for at least tSRC to activate the

reset output pulse. Include an internal 65 k

Ω pull-up resistor to VCC for each input.

Figure 6.

Timing waveforms

1.3.4

Adjustable delay of Smart Reset™ input (SRC pin)

This pin controls the setup time before the push-button action is validated by the reset

output. It is connected to an external capacitor (CSRC), which is tied to ground to provide the

desired value of setup time (tSRC).

Calculated tSRC and CSRC examples are given in Table 2. Refer also to Table 6.

AM00393

RST

SR0

SR1

tSRC

tREC

Table 2.

tSRC programmed by an ideal external capacitor

Calculated CSRC

value [µF]

Setup delay tSRC [s]

(1)(2)

Example calculations based on an ideal capacitor. During application design and component selection it

should be considered that the current flowing into the external tSRC programming capacitor (CSRC) is on

the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) and an adequate PCB

environment should be used to prevent tSRC accuracy from being affected. A recommended minimum

value of CSRC is 0.01 µF.

In case of repeated activations of the tSRC counter, an interval of 10 ms min. is needed between the

activations to fully discharge CSRC, so that the next tSRC is as specified.

Closest common

CSRC value [µF]

Min.

Typ.

Max.

0.2

0.22

0.3

4.5

0.33

0.6

0.56

110

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