STM6510 datasheet(5/26 Pages) STMICROELECTRONICS

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STM6510

Description

Doc ID 16788 Rev 2

5/26

Description

1.1

Smart Reset™ devices

The Smart Reset™ device family STM65xx provides a useful feature that ensures

inadvertent short reset push-button closures do not cause system resets. This is done by

implementing an extended Smart Reset™ input delay (tSRC). Once the valid Smart Reset™

input levels and setup delay are met, the device generates an output reset pulse with user-

programmable timeout period (tREC).

The typical application hookup shows that the dual Smart Reset™ inputs can be also

connected to the applications interrupt to allow the control of both the interrupt pin and the

hard reset functions. If the push-buttons are closed for a short time, the processor is only

interrupted. If the system still does not respond properly, holding the push-buttons for the

extended setup time (tSRC) causes a hard reset of the processor through the reset output.

The Smart Reset™ feature helps significantly increase system stability.

The STM65xx family of Smart Reset™ devices consists of low-current microprocessor reset

circuits targeted at applications such as MP3 players, portable navigation devices or mobile

phones, generally any application that requires delayed reset push-button(s) response for

improved system stability. The STM65xx devices feature single or dual Smart Reset™

inputs (SRx). The delayed Smart Reset™ setup time (tSRC) options are adjustable by

adding an external capacitor on the SRC pin or selectable by three-state logic. The delayed

setup period ignores switch closures shorter than tSRC, thus preventing undesired resets.

The STM65xx devices have active-low (optionally active-high) open-drain reset (RST)

output(s) with or without an internal pull-up resistor or push-pull as output options, with or

without the power-on reset function.

Some devices also have an undervoltage monitoring feature: the reset output is also

asserted when the monitored supply voltage VCC drops below the specified threshold. The

reset output remains asserted for the reset timeout period (tREC) after the monitored supply

voltage goes above the specified threshold.

1.2

STM6510

The STM6510 has two combined Smart Reset™ inputs (SR0 and SR1) with Smart Reset™

setup delay (tSRC) programmed by an external capacitor on the SRC pin. An additional

STM6510 feature is adjustable output reset pulse time tREC by adding an external capacitor

(CtREC).

Additionally, the VCC is monitored and if it drops below the selected VRST threshold, the

reset output goes active and remains active while VCC is below the VRST threshold, plus the

defined duration of the reset pulse tREC.

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