CDCE925PWR datasheet(18/27 Pages) TI

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CDCE925

CDCEL925

SCAS847F – JULY 2007 – REVISED MARCH 2010

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Table 10. PLL1 Configuration Register (continued)

OFFSET(1)

Bit(2)

Acronym

Default(3)

DESCRIPTION

18h

7:0

PLL1_0N [11:4

PLL1_0(5): 30-Bit Multiplier/Divider value for frequency fVCO1_0

004h

(for more information, see paragraph PLL Multiplier/Divider Definition).

19h

7:4

PLL1_0N [3:0]

3:0

PLL1_0R [8:5]

000h

1Ah

7:3

PLL1_0R[4:0]

2:0

PLL1_0Q [5:3]

10h

1Bh

7:5

PLL1_0Q [2:0]

4:2

PLL1_0P [2:0]

010b

fVCO1_0 range selection:

00 – fVCO1_0 < 125 MHz

01 – 125 MHz

≤ fVCO1_0 < 150 MHz

1:0

VCO1_0_RANGE

00b

10 – 150 MHz

≤ fVCO1_0 < 175 MHz

11 – fVCO1_0 ≥ 175 MHz

1Ch

7:0

PLL1_1N [11:4]

PLL1_1(5): 30-Bit Multiplier/Divider value for frequency fVCO1_1

004h

(for more information see paragraph PLL Multiplier/Divider Definition)

1Dh

7:4

PLL1_1N [3:0]

3:0

PLL1_1R [8:5]

000h

1Eh

7:3

PLL1_1R[4:0]

2:0

PLL1_1Q [5:3]

10h

1Fh

7:5

PLL1_1Q [2:0]

4:2

PLL1_1P [2:0]

010b

fVCO1_1 range selection:

00 – fVCO1_1 < 125 MHz

01 – 125 MHz

≤ fVCO1_1 < 150 MHz

1:0

VCO1_1_RANGE

00b

10 – 150 MHz

≤ fVCO1_1 < 175 MHz

11 – fVCO1_1 ≥ 175 MHz

(5)

PLL settings limits: 16

≤q≤63, 0≤p≤7, 0≤r≤511, 0<N<4096

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