EEPROM

Xin/CLK

Xout

VDD

GND

Vctr

VDDOUT

VCXO

XO

LVCMOS

Y2

Y1

Y3

LV

CMOS

Pdiv1

10-Bit

Y4

Y5

LV

CMOS

Pdiv5

7-Bit

Pdiv4

7-Bit

LV

CMOS

LV

CMOS

Pdiv3

7-Bit

Pdiv2

7-Bit

LV

CMOS

Programming

and

SDA/SCL

Register

InputClock

PLL Bypass

PLL 1

WithSSC

PLL Bypass

PLL 2

WithSSC

S0

S1/SDA

S2/SCL

CDCE925

CDCEL925

www.ti.com

SCAS847F – JULY 2007 – REVISED MARCH 2010

FUNCTIONAL BLOCK DIAGRAM for CDCE925, CDCEL925

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

VALUE

UNIT

Supply voltage range

–0.5 to 2.5

V

V

V

20

mA

Continuous output current

50

mA

Storage temperature range

–65 to 150

°C

Maximum junction temperature

125

°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2)

The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed.

(3)

SDA and SCL can go up to 3.6V as stated in the Recommended Operating Conditions table.

PACKAGE THERMAL RESISTANCE for TSSOP (PW) PACKAGE

(1)

over operating free-air temperature range (unless otherwise noted)

AIRFLOW

TSSOP16

PARAMETER

(lfm)

°C/W

0

101

150

85

Thermal Resistance Junction to Ambient

200

84

250

82

500

74

Thermal Resistance Junction to Case

—

42

Thermal Resistance Junction to Board

—

64

Thermal Resistance Junction to Top

—

1.0

Thermal Resistance Junction to Bottom

—

58

(1)

The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

Copyright © 2007–2010, Texas Instruments Incorporated

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Product Folder Link(s): CDCE925 CDCEL925