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EP3SL50 数据表(PDF) 79 Page - Altera Corporation

部件名 EP3SL50
功能描述  Stratix III Device Handbook, Volume 2
PDF  341 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP3SL50 数据表(HTML) 79 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–69
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
3.0-V
LVCMOS
GCLK
t
su
-0.817
-0.847
1.377
1.519
1.765
1.697
1.969
1.534
1.771
1.708
1.997
ns
t
h
0.931
0.973
-1.191 -1.310 -1.531 -1.478 -1.750 -1.314 -1.528 -1.479 -1.778
ns
GCLK
PLL
t
su
0.931
0.934
1.576
1.787
1.897
1.781
1.796
1.788
1.908
1.789
1.850
ns
t
h
-0.682
-0.673
1.377
1.519
1.765
1.697
1.969
1.534
1.771
1.708
1.997
ns
2.5 V
GCLK
t
su
-0.805
-0.840
1.518
1.758
1.994
1.874
1.798
1.758
1.917
1.798
1.849
ns
t
h
0.919
0.966
1.447
1.676
1.892
1.823
2.114
1.723
1.933
1.867
2.146
ns
GCLK
PLL
t
su
0.943
0.941
-1.259 -1.469 -1.662 -1.607 -1.898 -1.507 -1.694 -1.641 -1.931
ns
t
h
-0.694
-0.680
1.518
1.758
1.994
1.874
1.798
1.758
1.917
1.798
1.849
ns
1.8 V
GCLK
t
su
-0.946
-0.899
1.542
1.790
2.062
1.942
1.866
1.789
1.982
1.863
1.914
ns
t
h
0.914
0.891
1.423
1.644
1.824
1.755
2.046
1.692
1.868
1.802
2.081
ns
GCLK
PLL
t
su
1.060
1.028
-1.235 -1.437 -1.594 -1.539 -1.830 -1.476 -1.629 -1.576 -1.866
ns
t
h
-0.936
-0.888
1.621
1.891
2.221
2.101
2.025
1.885
2.137
2.018
2.069
ns
1.5 V
GCLK
t
su
0.924
0.902
1.344
1.543
1.665
1.596
1.887
1.596
1.713
1.647
1.926
ns
t
h
1.050
1.017
-1.156 -1.336 -1.435 -1.380 -1.671 -1.380 -1.474 -1.421 -1.711
ns
GCLK
PLL
t
su
-0.876
-0.835
1.662
1.896
2.117
2.001
2.016
1.900
2.125
2.006
2.067
ns
t
h
0.984
0.955
1.291
1.410
1.545
1.477
1.749
1.422
1.554
1.491
1.780
ns
1.2 V
GCLK
t
su
0.990
0.964
-1.118 -1.309 -1.430 -1.374 -1.667 -1.348 -1.467 -1.413 -1.704
ns
t
h
-0.747
-0.781
1.659
-1.309 -1.430 -1.374 -1.667 -1.348 -1.467 -1.413 -1.704
ns
GCLK
PLL
t
su
1.000
0.999
1.306
1.514
1.658
1.589
1.879
1.562
1.703
1.638
1.915
ns
t
h
0.862
0.908
-1.118
1.918
2.223
2.104
2.029
1.917
2.144
2.026
2.076
ns
SSTL-2
CLASS I
GCLK
t
su
-0.747
-0.781
1.659
1.918
2.223
2.104
2.029
1.917
2.144
2.026
2.076
ns
t
h
1.000
0.999
1.306
-1.472 -1.722 -1.633 -1.557 -1.461 -1.635 -1.548 -1.601
ns
GCLK
PLL
t
su
0.862
0.908
-1.118 -1.309 -1.430 -1.374 -1.667 -1.348 -1.467 -1.413 -1.704
ns
t
h
-0.850
-0.800
1.659
1.514
1.658
1.589
1.879
1.562
1.703
1.638
1.915
ns
SSTL-2
CLASS II
GCLK
t
su
1.010
0.990
1.306
1.918
2.223
2.104
2.029
1.917
2.144
2.026
2.076
ns
t
h
0.964
0.929
-1.118 -1.472 -1.722 -1.633 -1.557 -1.461 -1.635 -1.548 -1.601
ns
GCLK
PLL
t
su
-0.850
-0.800
-1.276 -1.299 -1.412 -1.356 -1.649 -1.337 -1.450 -1.396 -1.687
ns
t
h
1.010
0.990
-1.105
1.504
1.640
1.571
1.861
1.551
1.686
1.621
1.898
ns
SSTL-18
CLASS I
GCLK
t
su
0.964
0.929
1.294
1.928
2.241
2.122
2.047
1.928
2.161
2.043
2.093
ns
t
h
-0.836
-0.788
1.659
1.928
2.241
2.122
2.047
1.928
2.161
2.043
2.093
ns
GCLK
PLL
t
su
1.024
1.002
1.306
-1.482 -1.740 -1.651 -1.575 -1.472 -1.652 -1.565 -1.618
ns
t
h
0.950
0.917
-1.118 -1.299 -1.412 -1.356 -1.649 -1.337 -1.450 -1.396 -1.687
ns
SSTL-18
CLASS II
GCLK
t
su
-0.850
-0.800
1.659
-1.472 -1.722 -1.633 -1.557 -1.461 -1.635 -1.548 -1.601
ns
t
h
1.010
0.990
1.306
-1.309 -1.430 -1.374 -1.667 -1.348 -1.467 -1.413 -1.704
ns
GCLK
PLL
t
su
0.964
0.929
-1.118
1.514
1.658
1.589
1.879
1.562
1.703
1.638
1.915
ns
t
h
-0.850
-0.800
-1.276
1.918
2.223
2.104
2.029
1.917
2.144
2.026
2.076
ns
Table 1–52. EP3SL70 Row Pins Input Timing Parameters (Part 2 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V



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