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EP3SL50 数据表(PDF) 32 Page - Altera Corporation |
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EP3SL50 数据表(HTML) 32 Page - Altera Corporation |
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32 / 341 page  1–22 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics Stratix III Device Handbook, Volume 2 © July 2010 Altera Corporation LVDS_E_1R -f HSDR (data rate) SERDES factor J = 4 to 10 (4) — 311 (4) — 200 (4) —200 (4) — 200 Mbps t x Jitter (5) Total Jitter for Data Rate, 600 Mbps – 1.6 Gbps — — 160 — — 160 — — 160 — — 160 ps Total Jitter for Data Rate, <600 Mbps — — 0.1 — — 0.1 — — 0.1 — — 0.1 UI t DUTY T X output duty cycle for both True and Emulated Differential I/O 45 50 55 45 50 55 45 50 55 45 50 55 % tRISE & tFALL True Differential I/O Standards — — 160 — — 200 — — 200 — — 200 ps t RISE & tFALL Emulated Differential I/O Standards with Three External Output Resistor Network — — 310 — — 310 — — 350 — — 350 ps t RISE & tFALL Emulated Differential I/O Standards with One External Output Resistor Network — — 460 — — 500 — — 500 — — 500 ps TCCS True Differential I/O Standards — — 100 — — 100 — — 100 — — 100 ps TCCS Emulated Differential I/O Standards — — 250 — — 250 — — 250 — — 250 ps Receiver f HSDRDPA (data rate) SERDES factor J = 3 to 10 150 — 1600 150 — 1250 150 — 1250 150 — 1250 Mbps f HSDR (data rate) SERDES factor J = 3 to 10 (4) — (6) (4) — (6) (4) — (6) (4) — (6) Mbps SERDES factor J = 2, Uses DDR Registers (4) — (6) (4) — (6) (4) — (6) (4) — (6) Mbps SERDES factor J = 1, Uses an SDR Register (4) — (6) (4) — (6) (4) — (6) (4) — (6) Mbps DPA DPA run length — — — 10000 — — 10000 — — 10000 — — 10000 UI Soft CDR mode Soft-CDR PPM tolerance — — — 300 — — 300 — — 300 — — 300 ± PPM Table 1–25. True and Emulated LVDS Specifications for Stratix III Devices (Note 1), (2) (Part 2 of 3) Symbol Conditions C2 C3, I3 C4, I4 C4L, I4L |
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