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EP3SL50 数据表(PDF) 91 Page - Altera Corporation |
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EP3SL50 数据表(HTML) 91 Page - Altera Corporation |
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91 / 341 page  Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics 1–81 I/O Timing © July 2010 Altera Corporation Stratix III Device Handbook, Volume 2 1.8-V HSTL CLASS I 4mA GCLK tco 3.021 3.241 4.580 4.964 5.472 5.336 5.548 5.097 5.606 5.471 5.617 ns GCLK PLL t co 1.314 1.486 1.882 1.968 2.156 2.174 2.121 2.098 2.302 2.319 2.110 ns 6mA GCLK t co 3.014 3.229 4.571 4.963 5.471 5.335 5.547 5.096 5.606 5.471 5.617 ns GCLK PLL tco 1.302 1.480 1.880 1.967 2.148 2.166 2.113 2.090 2.295 2.312 2.103 ns 8mA GCLK t co 3.005 3.217 4.563 4.956 5.464 5.328 5.540 5.089 5.599 5.464 5.610 ns GCLK PLL t co 1.289 1.472 1.873 1.960 2.140 2.158 2.105 2.082 2.287 2.304 2.095 ns 10mA GCLK t co 3.008 3.219 4.565 4.959 5.468 5.332 5.544 5.092 5.602 5.467 5.613 ns GCLK PLL t co 1.292 1.474 1.876 1.963 2.143 2.161 2.108 2.085 2.290 2.307 2.098 ns 12mA GCLK tco 3.004 3.214 4.563 4.962 5.471 5.335 5.547 5.095 5.607 5.472 5.618 ns GCLK PLL t co 1.288 1.471 1.878 1.966 2.143 2.161 2.108 2.085 2.291 2.308 2.099 ns 1.8-V HSTL CLASS II 16mA GCLK t co 3.012 3.218 4.558 4.959 5.467 5.331 5.543 5.091 5.601 5.466 5.612 ns GCLK PLL t co 1.296 1.479 1.876 1.963 2.134 2.152 2.099 2.078 2.280 2.297 2.088 ns 1.5-V HSTL CLASS I 4mA GCLK t co 3.027 3.248 4.591 4.974 5.483 5.347 5.559 5.106 5.617 5.482 5.628 ns GCLK PLL t co 1.321 1.492 1.891 1.978 2.171 2.189 2.136 2.110 2.316 2.333 2.124 ns 6mA GCLK t co 3.021 3.238 4.587 4.976 5.485 5.349 5.561 5.108 5.620 5.485 5.631 ns GCLK PLL t co 1.309 1.487 1.892 1.980 2.167 2.185 2.132 2.107 2.313 2.330 2.121 ns 8mA GCLK tco 3.017 3.233 4.581 4.971 5.480 5.344 5.556 5.103 5.614 5.479 5.625 ns GCLK PLL t co 1.305 1.483 1.887 1.975 2.161 2.179 2.126 2.101 2.307 2.324 2.115 ns 1.2-V HSTL CLASS I 4mA GCLK t co 3.029 3.247 4.602 4.990 5.502 5.366 5.578 5.122 5.636 5.501 5.647 ns GCLK PLL t co 1.320 1.494 1.904 1.994 2.189 2.207 2.154 2.124 2.333 2.350 2.141 ns 6mA GCLK t co 3.020 3.235 4.591 4.981 5.493 5.357 5.569 5.113 5.627 5.492 5.638 ns GCLK PLL t co 1.308 1.486 1.895 1.985 2.177 2.195 2.142 2.113 2.322 2.339 2.130 ns 8mA GCLK t co 3.019 3.233 4.595 4.989 5.502 5.366 5.578 5.122 5.637 5.502 5.648 ns GCLK PLL t co 1.305 1.486 1.902 1.993 2.183 2.201 2.148 2.119 2.329 2.346 2.137 ns 3.0-V PCI — GCLK tco 3.076 3.300 4.588 4.978 5.480 5.342 5.550 5.105 5.610 5.474 5.621 ns GCLK PLL t co 1.429 1.614 1.966 2.045 2.237 2.256 2.174 2.160 2.357 2.374 2.165 ns 3.0-V PCI-X — GCLK t co 3.076 3.300 4.588 4.978 5.480 5.342 5.550 5.105 5.610 5.474 5.621 ns GCLK PLL t co 1.429 1.614 1.966 2.045 2.237 2.256 2.174 2.160 2.357 2.374 2.165 ns Table 1–54. EP3SL70 Row Pins Output Timing Parameters (Part 4 of 4) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V |
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