SC403

6

Electrical Characteristics (continued)

Parameter

Conditions

Min

Typ

Max

Units

Logic Inputs/Outputs (continued)

EN/PSV Input for Disabling Switcher

Maximum level

0.4

V

Minimum level

0

EN/PSV Input Bias Current

EN/PSV= VDD or AGND

-8

+8

μA

ENL Input Bias Current

V

11

18

μA

FBL, FB Input Bias Current

FBL, FB = VDD or AGND

-1

+1

μA

Linear Regulator (The LDO is shorted to the VDD pin internally.)

FBL Accuracy

LDO load = 10mA

0.735

0.75

0.765

V

LDO Current Limit

Short-circuit protection, V

65

mA

Start-up and foldback, V

0.75 < V

115

Operating current limit, V

V

135

200

-140

+140

mV

-450

+450

mV

LDO to VOUT Switch-over Resistance

V

2

Ω

From V

1.2

V

Notes:

(1) V

(2) For VDD less than 4.5V, the on-time may be limited by the VDD supply voltage and by the V

section in the applications Information.

(3) The switch-over threshold is the maximum voltage differential between the VDD and VOUT pins which ensures that LDO will internally switch-

over to VOUT. The non-switch-over threshold is the minimum voltage differential between the LDO and VOUT pins which ensures that LDO

will not switch-over to VOUT.

(4) The LDO drop out voltage is the voltage at which the LDO output drops 2% below the no load regulation value.