SC403 datasheet(22/32 Pages) SEMTECH

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SC403

Applications Information (continued)

In many applications, the EN/PSV pin will be pulled high to

the VDD node to allow control of the PWM and LDO ENL

pin. If the switch over feature is used, this circuit must be

implemented with caution or the circuit may be damaged.

In the case where the ENL pin is being controlled by a GPIO

signal or is tied directly to the input voltage, the ENL pin can

be pulled low while the PWM is still generating an output

voltage that is seen across one of the switch-over diodes.

This may result in the VDD node being held above its UVLO

threshold while the LDO is deactivated. Operating in this

way can potentially damage the part.

In the case where the ENL pin is used to control the input

UVLO, it is acceptable to connect EN/PSV directly to the

VDD node.

It is not recommended to use the switch-over feature for

an output voltage less than 3V since this does not provide

sufficient voltage for the gate-source drive to the internal

p-channel switch-over MOSFET.

Switch-over MOSFET Parasitic Diode

The switch-over MOSFET contains a parasitic diode that is

inherent to its construction, as shown in Figure 12.

Switchover

MOSFET

Parasitic diode

VDD

LDO

VOUT

Switchover

control

Figure 12— Switch-over MOSFET Parasitic Diodes

If V

OUT is higher than VDD, then the diode will turn on and

the SC403 operating current will flow through this diode.

This has the potential of damaging the device.

There are some important design rules that must be fol-

lowed to prevent forward bias of this diode. The following

condition, V

DD ≥ VOUT needs to be satisfied in order for the

parasitic diode to stay off and prevent damaging the

device. Many applications connect the EN pin to V5V and

control the on/off of the LDO and PWM simultaneously

with the ENL pin. This allows one signal to control both

the bias and power output of the SC414. When V

OUT > 3.0V

this configuration can cause problems due to the parasitic

diodes in the LDO switchover circuitry. After the V

OUT >

3.0V PWM output is up and running the switchover diodes

can hold up V5V > UVLO even if the ENL pin is grounded,

turning off the LDO. Operating in this way can potentially

damage the part.

Design Procedure

When designing a switch mode supply the input voltage

range, load current, switching frequency, and inductor

ripple current must be specified.

The maximum input voltage (V

INMAX) is the highest speci-

fied input voltage. The minimum input voltage ( V

INMIN) is

determined by the lowest input voltage after evaluating

the voltage drops due to connectors, fuses, switches, and

PCB traces.

The following parameters define the design.

Nominal output voltage (V

OUT)

Static or DC output tolerance

Transient response

Maximum load current (I

OUT)

There are two values of load current to evaluate — con-

tinuous load current and peak load current. Continuous

load current relates to thermal stresses which drive the

selection of the inductor and input capacitors. Peak load

current determines instantaneous component stresses and

filtering requirements such as inductor saturation, output

capacitors, and design of the current limit circuit.

The following values are used in this design.

IN = 12V + 10%

OUT = 1.5V + 4%

SW = 300kHz

Load = 6A maximum

Frequency Selection

Selection of the switching frequency requires making a

trade-off between the size and cost of the external filter

components (inductor and output capacitor) and the

power conversion efficiency.

•

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