PRELIMINARY SPECIFICATION (V1.5)

FREQUENCY SYNTHESIZER

KB8821/22/23

12

99-06-15

Programmable Counter(N Counter)

If the Control Bits are 10(IF) or 11(RF), data is transferred from the 20-bit shift register into the N-latch. N Counter

consists of 7-bit swallow counter(A counter) and 11-bit main counter(B counter). Serial data format is shown

below.

♦ 7-Bit Swallow Counter Division Ratio(A Counter)

RF

IF

Division ratio : 0 to 127

Division ratio : 0 to 15

B

≥ A

B

≥ A

X = DON’T CARE condition

♦ 11-Bit Main Counter Division Ratio(B Counter)

Division ratio : 3 to 2047

C1

C2

N

1

N

2

N

3

N

4

N

5

N

6

N

7

N

8

N

9

N

10

N

11

N

12

N

13

N

14

N

15

N

16

N

17

N

18

N

19

N

20

Division

Ratio(A)

N

7

N

6

N

5

N

4

N

3

N

2

N

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

1

•

•

•

•

•

•

•

•

127

1

1

1

1

1

1

1

Division

Ratio

N

18

N

17

N

16

N

15

N

14

N

13

N

12

N

11

N

10

N

9

N

8

3

0

0

0

0

0

0

0

0

0

1

1

4

0

0

0

0

0

0

0

0

1

0

0

•

•

•

•

•

•

•

•

•

•

•

•

2047

1

1

1

1

1

1

1

1

1

1

1

Division

Ratio(A)

N

7

N

6

N

5

N

4

N

3

N

2

N

1

0

X

X

X

0

0

0

0

1

X

X

X

0

0

0

1

•

•

•

•

•

•

•

•

15

X

X

X

1

1

1

1

LSB

MSB

Division Ratio of the N Counter, N

Control Bits

Program

Modes