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PT8300 V1.8

- 7 -

February, 2006

16-Bit I/O Expander IC

PT8300

DATA TIMING DIAGRAM

READ

SINGLE MODE (P0-P7 = Output [Write], P8-P15 = Input [Read])

Latch

CLK

DI1

FFH (P 15 to P 8)

00H ~FFH (P7 to P 0)

IR RE LE VA N T

P 15~P 8

DO2

1

2

3

4

5

67

8

9

10

11

12

13

14

15

16

CASCADE MODE (P0-P7 [Master] = Output [Write], P8-P15 [Master] = Input [Read],

P0-P7 [Slave] = Output [Write], P8-P15 [Slave] = Input [Read])

La tc h

CL K

DI1

F F H(Slave P 15 to P 8)

0 0H~ FF H( Sl a ve P 7 t o P0 )

IR REL E VA NT

IR R ELE VA N T

F F H (M aste r P 1 5 to P 8)

0 0H ~ FF H( Mas te r P 7 to P0)

P8 ~P15 (Mas te r)

P8 ~P15 (Slave)

DO 2

1

2

3

4

5 67 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32