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REJ03B0253-0110

Rev.1.10

Page 19 of 95

Jun 23, 2010

R32C/116 Group

1. Overview

1.5

Pin Definitions and Functions

Table 1.14 to Table 1.18 show the pin definitions and functions.

Notes:

Pins

INT6 to INT8 are available in the 144-pin package only.

Pins D16 to D31 are available in the 144-pin package only.

Table 1.14

Pin Definitions and Functions (1/4)

Function

Symbol

I/O

Description

Power supply

VCC, VSS

Applicable as follows: VCC = 3.0 to 5.5 V, VSS = 0 V

Connecting pins

for decoupling

capacitor

VDC0, VDC1

—

A decoupling capacitor for internal voltage should be

connected between VDC0 and VDC1

Analog power

supply

AVCC, AVSS

Power supply for the A/D converter. AVCC and AVSS

should be connected to VCC and VSS, respectively

Reset input

RESET

The MCU is reset when this pin is driven low

CNVSS

This pin should be connected to VSS via a resistor

Debug port

NSD

I/O

This pin is to communicate with a debugger. It should be

connected to VCC via a resistor of 1 to 4.7 k

Main clock input

XIN

Input/output for the main clock oscillator. A crystal, or a

ceramic resonator should be connected between pins XIN

and XOUT. An external clock should be input at the XIN

while leaving the XOUT open

Main clock output XOUT

Sub clock input

XCIN

Input/output for the sub clock oscillator. A crystal oscillator

should be connected between pins XCIN and XCOUT. An

external clock should be input at the XCIN while leaving the

XCOUT open

Sub clock output XCOUT

BCLK output

BCLK

BCLK output

Clock output

CLKOUT

Output of the clock with the same frequency as low speed

clocks, f8, or f32

External interrupt

input

INT0 to INT8 (1)

Input for external interrupts

NMI input

P8_5/

NMI

Input for NMI

Key input interrupt

KI0 to KI3

Input for the key input interrupt

Bus control pins

D0 to D7

I/O

Input/output of data (D0 to D7) while accessing an external

memory space with a separate bus

D8 to D15

I/O

Input/output of data (D8 to D15) while accessing an

external memory space with 16-bit or 32-bit separate bus

D16 to D31 (2)

I/O

Input/output of data (D16 to D31) while accessing an

external memory space with 32-bit separate bus

A0 to A23

Output of address bits A0 to A23

A0/D0 to A7/D7

I/O

Output of address bits (A0 to A7) and input/output of data

(D0 to D7) by time-division while accessing an external

memory space with multiplexed bus

A8/D8 to

A15/D15

I/O

Output of address bits (A8 to A15) and input/output of data

(D8 to D15) by time-division while accessing an external

memory space with 16-bit or 32-bit multiplexed bus

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