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LTM4618

4618f

Figure 20. Recommended PCB Layout Example

4618 F20

VIN

PGND

CNTRL

ABC

COUT

VOUT

PGND

APPLICATIONS INFORMATION

EMI Section

The LTM4618 has been evaluated for CISPR22 A and B

Radiated EMI and CISPR25 Conducted EMI. The CISPR25

Conducted EMI test was performed with an input π ﬁlter

as shown in Figure 17. An RC snubber circuit is optionally

used from the SW pin to the PGND pin to improve the higher

frequency attenuation and EMI limit guard band. Figure 18

shows the CISPR25 conducted emissions plot for 26.5V

input to 3.3V output at 5A load. Several conditions were

evaluated, and Figure 18 results are from the worst-case

condition. The input π ﬁlter is used to attenuate the reﬂected

noise from the regulator input, and is primarily utilized

when the power regulators are closed to the input power

feed to a board, like the input power connectors. If the

regulator design is placed out on the center of the system

board, then the input π ﬁlter may not be needed because

all of the extra board capacitance and the inductive planes

will provide ﬁltering for reﬂected emissions. If the system

board has noise sensitive circuitry that is powered from

the same voltage rail as the regulators are, then an input

π ﬁlter is a good idea to keep regulator noise from cor-

rupting the noise sensitive circuitry on the system board.

Figure 19 shows the CISPR22 B Radiated EMI plots. The

input π ﬁlter is used to attenuate the reﬂected noise from

propagating out onto the input power cables, thus pos-

sibly causing radiated EMI issues. An RC snubber circuit

is optionally used from the SW pin to the PGND pin to

improve the higher frequency attenuation and EMI limit

guard band. A placeholder can accommodate the RSNUB

and CSNUB components with 1.2Ω and 470pF. These

components are probably not necessary, but can be used

or adjusted to improve the radiated limit guard bands at

the higher frequencies by attenuating any switch node

ringing due to parasitic values in the high speed switching

paths. It is important to follow the recommended layout

guidelines and use good X5R or X7R ceramic capacitors

to get good results.

Layout Checklist/Example

The high integration of LTM4618 makes the PC board layout

very simple and easy. However, to optimize its electrical

and thermal performance, some layout considerations

are still necessary.

• Use large PCB copper areas for high current path,

including VIN, PGND and VOUT. It helps to minimize

the PCB conduction loss and thermal stress.

• Test points can be placed on signal pin for monitor-

ing during testing.

• Place high frequency ceramic input and output

capacitors next to the VIN, PGND and VOUT pins to

minimize high frequency noise.

• Place a dedicated power ground layer underneath the

unit.

• To minimize the via conduction loss and reduce mod-

ule thermal stress, use multiple vias for interconnec-

tion between top layer and other power layers.

• Do not put vias directly on the pad, unless they are

capped.

• Use a separated SGND ground copper area for com-

ponents connected to signal pins. Connect the SGND

to PGND underneath the unit.

Figure 20 gives a good example of the recommended

layout.

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