ST6253C datasheet(44/83 Pages) STMICROELECTRONICS

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ST6253C ST6263C ST6263B ST6260C ST6260B

TIMER (Cont’d)

A write to the TCR register will predominate over

the 8-bit counter decrement to 00h function, i.e. if a

write and a TCR register decrement to 00h occur

simultaneously, the write will take precedence,

and the TMZ bit is not set until the 8-bit counter

reaches 00h again. The values of the TCR and the

PSC registers can be read accurately at any time.

4.2.4 Timer Registers

Timer Status Control Register (TSCR)

Address: 0D4h

—

Read/Write

Bit 7 = TMZ: Timer Zero bit

A low-to-high transition indicates that the timer

count register has decrement to zero. This

bit

must be cleared by user software before starting a

new count.

Bit 6 = ETI: Enable Timer Interrup

When set, enables the timer interrupt request

(vector #4). If ETI=0 the timer interrupt is disabled.

If ETI=1 and TMZ=1 an interrupt request is gener-

ated.

Bit 5 = D5: Reserved

Must be set to “1”.

Bit 4 = D4

Do not care.

Bit 3 = PSI: Prescaler Initialize Bit

Used to initialize the prescaler and inhibit its count-

ing. When PSI=“0” the prescaler is set to 7Fh and

the counter is inhibited. When PSI=“1” the prescal-

er is enabled to count downwards. As long as

PSI=“0” both counter and prescaler are not run-

ning.

Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Se-

lect. These bits select the division ratio of the pres-

caler register.

Table 12. Prescaler Division Factors

Timer Counter Register (TCR)

Address: 0D3h

—

Read/Write

Bit 7-0 = D7-D0: Counter Bits.

Prescaler Register PSC

Address: 0D2h

—

Read/Write

Bit 7 = D7: Always read as "0".

Bit 6-0 = D6-D0: Prescaler Bits.

TMZ

ETI

PSI

PS2

PS1

PS0

PS2

PS1

PS0

Divided by

128

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