ST6253C datasheet(45/83 Pages) STMICROELECTRONICS

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ST6253C ST6263C ST6263B ST6260C ST6260B

4.3 AUTO-RELOAD TIMER

The Auto-Reload Timer (AR Timer) on-chip pe-

ripheral consists of an 8-bit timer/counter with

compare and capture/reload capabilities and of a

7-bit prescaler with a clock multiplexer, enabling

the clock input to be selected as fINT, fINT/3 or an

external clock source. A Mode Control Register,

ARMC, two Status Control Registers, ARSC0 and

ARSC1, an output pin, ARTIMout, and an input

pin, ARTIMin, allow the Auto-Reload Timer to be

used in 4 modes:

– Auto-reload (PWM generation),

– Output compare and reload on external event

(PLL),

– Input capture and output compare for time meas-

urement.

– Input capture and output compare for period

measurement.

The AR Timer can be used to wake the MCU from

WAIT mode either with an internal or with an exter-

nal clock. It also can be used to wake the MCU

from STOP mode, if used with an external clock

signal connected to the ARTIMin pin. A Load reg-

ister allows the program to read and write the

counter on the fly.

4.3.1 AR Timer Description

The AR COUNTER is an 8-bit up-counter incre-

mented on the input clock’s rising edge. The coun-

ter is loaded from the ReLoad/Capture Register,

ARRC, for auto-reload or capture operations, as

well as for initialization. Direct access to the AR

counter is not possible; however, by reading or

writing the ARLR load register, it is possible to

read or write the counter’s contents on the fly.

The AR Timer’s input clock can be either the inter-

nal clock (from the Oscillator Divider), the internal

clock divided by 3, or the clock signal connected to

the ARTIMin pin. Selection between these clock

sources is effected by suitably programming bits

CC0-CC1 of the ARSC1 register. The output of the

AR Multiplexer feeds the 7-bit programmable AR

Prescaler, ARPSC, which selects one of the 8

available taps of the prescaler, as defined by

PSC0-PSC2 in the AR Mode Control Register.

Thus the division factor of the prescaler can be set

to 2n (where n = 0, 1,..7).

The clock input to the AR counter is enabled by the

TEN (Timer Enable) bit in the ARMC register.

When TEN is reset, the AR counter is stopped and

the prescaler and counter contents are frozen.

When TEN is set, the AR counter runs at the rate

of the selected clock source. The counter is

cleared on system reset.

The AR counter may also be initialized by writing

to the ARLR load register, which also causes an

immediate copy of the value to be placed in the AR

counter, regardless of whether the counter is run-

ning or not. Initialization of the counter, by either

method, will also clear the ARPSC register, where-

upon counting will start from a known value.

4.3.2 Timer Operating Modes

Four different operating modes are available for

the AR Timer:

Auto-reload Mode with PWM Generation. This

mode allows a Pulse Width Modulated signal to be

generated on the ARTIMout pin with minimum

Core processing overhead.

The free running 8-bit counter is fed by the pres-

caler’s output, and is incremented on every rising

edge of the clock signal.

When a counter overflow occurs, the counter is

automatically reloaded with the contents of the Re-

load/Capture Register, ARCC, and ARTIMout is

set. When the counter reaches the value con-

tained in the compare register (ARCP), ARTIMout

is reset.

On overflow, the OVF flag of the ARSC0 register is

set and an overflow interrupt request is generated

if the overflow interrupt enable bit, OVIE, in the

Mode Control Register (ARMC), is set. The OVF

flag must be reset by the user software.

When the counter reaches the compare value, the

CPF flag of the ARSC0 register is set and a com-

pare interrupt request is generated, if the Compare

Interrupt enable bit, CPIE, in the Mode Control

tine may then adjust the PWM period by loading a

new value into ARCP. The CPF flag must be reset

by user software.

The PWM signal is generated on the ARTIMout

pin (refer to the Block Diagram). The frequency of

this signal is controlled by the prescaler setting

and by the auto-reload value present in the Re-

load/Capture register, ARRC. The duty cycle of

the PWM signal is controlled by the Compare Reg-

ister, ARCP.

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