ST6253C datasheet(49/83 Pages) STMICROELECTRONICS

49 / 83 page

49/83

ST6253C ST6263C ST6263B ST6260C ST6260B

AUTO-RELOAD TIMER (Cont’d)

4.3.3 AR Timer Registers

AR Mode Control Register (ARMC)

Address: D5h

—

Read/Write

Reset status: 00h

The AR Mode Control Register ARMC is used to

program the different operating modes of the AR

Timer, to enable the clock and to initialize the

counter. It can be read and written to by the Core

and it is cleared on system reset (the AR Timer is

disabled).

Note: Care should be taken when writing to the

ARMC register while AR Timer is running: if a

PWM signal is being output while the ARMC regis-

ter is overwritten with its previous value, ARTIMout

pin remains at its previous state for a programmed

time equal to tHIGH (refer to Figure 29). Then, a

new count starts.

Bit 7 = TLCD: Timer Load Bit. This bit, when set,

will cause the contents of ARRC register to be

loaded into the counter and the contents of the

prescaler register, ARPSC, are cleared in order to

initialize the timer before starting to count. This bit

is write-only and any attempt to read it will yield a

logical zero.

Bit 6 = TEN: Timer Clock Enable. This bit, when

set, allows the timer to count. When cleared, it will

stop the timer and freeze ARPSC and ARTSC.

Bit 5 = PWMOE: PWM Output Enable. This bit,

when set, enables the PWM output on the ARTI-

Mout pin. When reset, the PWM output is disabled.

Bit 4 = EIE: External Interrupt Enable. This bit,

when set, enables the external interrupt request.

When reset, the external interrupt request is

masked. If EIE is set and the related flag, EF, in

the ARSC0 register is also set, an interrupt re-

quest is generated.

Bit 3 = CPIE: Compare Interrupt Enable. This bit,

when set, enables the compare interrupt request.

If CPIE is reset, the compare interrupt request is

masked. If CPIE is set and the related flag, CPF, in

the ARSC0 register is also set, an interrupt re-

quest is generated.

Bit 2 = OVIE: Overflow Interrupt. This bit, when

set, enables the overflow interrupt request. If OVIE

is reset, the compare interrupt request is masked.

If OVIE is set and the related flag, OVF in the

ARSC0 register is also set, an interrupt request is

generated.

Bit 1-0 = ARMC1-ARMC0: Mode Control Bits 1-0.

These are the operating mode control bits. The fol-

lowing bit combinations will select the various op-

erating modes:

AR Timer Status/Control Registers ARSC0 &

ARSC1. These registers contain the AR Timer sta-

tus information bits and also allow the program-

ming of clock sources, active edge and prescaler

multiplexer setting.

ARSC0 register bits 0,1 and 2 contain the interrupt

flags of the AR Timer. These bits are read normal-

ly. Each one may be reset by software. Writing a

one does not affect the bit value.

AR Status Control Register 0 (ARSC0)

Address: D6h

—

Read/Clear

Bits 7-3 = D7-D3: Unused

Bit 2 = EF: External Interrupt Flag. This bit is set by

any active edge on the external ARTIMin input pin.

The flag is cleared by writing a zero to the EF bit.

Bit 1 = CPF: Compare Interrupt Flag. This bit is set

if the contents of the counter and the ARCP regis-

ter are equal. The flag is cleared by writing a zero

to the CPF bit.

Bit 0 = OVF: Overflow Interrupt Flag. This bit is set

by a transition of the counter from FFh to 00h

(overflow). The flag is cleared by writing a zero to

the OVF bit.

TCLD

TEN

PWMOE

EIE

CPIE

OVIE ARMC1 ARMC0

ARMC1

ARMC0

Operating Mode

Auto-reload Mode

Capture Mode

Capture Mode with Reset

of ARTC and ARPSC

Load on External Edge

Mode

CPF

OVF

ST6253C 数据表(PDF) 49 Page - STMicroelectronics

ST6253C 数据表(HTML) 49 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

数据表下载