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74ACT715-R 数据表(PDF) 12 Page - Fairchild Semiconductor |
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74ACT715-R 数据表(HTML) 12 Page - Fairchild Semiconductor |
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12 / 18 page ![]() ©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74ACT715, 74ACT715-R Rev. 1.3 12 RS170 Horizontal Data RS170 Verticle Data Signal Width µs %H Specification (µs) HFP 22 Clocks 1.536 1.5 ± 0.1 HSYNC Width 68 Clocks 4.749 7.47 4.7 ± 0.1 HBLANK Width 156 Clocks 10.895 17.15 10.9 ± 0.2 HDRIVE Width 91 Clocks 6.356 10.00 0.1H ± 0.005H HEQP Width 34 Clocks 2.375 3.74 2.3 ± 0.1 HSERR Width 68 Clocks 4.749 7.47 4.7 ± 0.1 HPER iod 910 Clocks 63.556 100 Signal Width µs %H Specification (µs) VFP 3 Lines 190.67 6 EQP Pulses VSYNC Width 3 Lines 190.67 6 Serration Pulses VBLANK Width 20 Lines 1271.12 7.62 0.075V ± 0.005V VDRIVE Width 11.0 Lines 699.12 4.20 0.04V ± 0.006V VEQP Intrvl 9 Lines 3.63 9 Lines/Field VPERiod (field) 262.5 Lines 16.683 ms 16.683ms/Field VPERiod (frame) 525 Lines 33.367 ms 33.367ms/Frame |
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