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74ACT715-R 数据表(PDF) 14 Page - Fairchild Semiconductor |
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74ACT715-R 数据表(HTML) 14 Page - Fairchild Semiconductor |
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14 / 18 page ![]() ©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74ACT715, 74ACT715-R Rev. 1.3 14 AC Operating Requirements Note: 3. Removal of Vectored Reset or Restart to Clock. Capacitance Figure 6. AC Specifications Symbol Parameter VCC (V) TA = +25°C TA = –40°C to +85°C Units Typ. Guaranteed Minimums Control Setup Time: 5.0 tsc ADDR/DATA to LOAD– 3.0 4.0 4.5 ns tsc L/HBYTE to LOAD– 3.0 4.0 4.5 ns tsd Data Setup Time: D7–D0 to LOAD+ 5.0 2.0 4.0 4.5 ns Control Hold Time: 5.0 thc LOAD– to ADDR/DATA 0 1.0 1.0 ns thc LOAD– to L/HBYTE 0 1.0 1.0 ns thd Data Hold Time: LOAD+ to D7–D0 5.0 1.0 2.0 2.0 ns trec LOAD+ to CLK(3) 5.0 5.5 7.0 8.0 ns Load Pulse Width: 5.0 twld– LOW 3.0 5.5 5.5 ns twld+ HIGH 3.0 5.0 7.5 ns twclr CLR Pulse Width HIGH 5.0 5.5 6.5 9.5 ns twck CLOCK Pulse Width (HIGH or LOW) 5.0 2.5 3.0 3.5 ns Symbol Parameter Conditions Typ. Units CIN Input Capacitance VCC = 5.0V 7.0 pF CPD Power Dissipation Capacitance VCC = 5.0V 17.0 pF |
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