M95010-R datasheet(22/43 Pages) STMICROELECTRONICS

22 / 43 page

Instructions

M95040, M95020, M95010

22/43

Doc ID 6512 Rev 8

6.6

Write to Memory Array (WRITE)

As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven

low. The bits of the instruction byte, address byte, and at least one data byte are then shifted

in, on Serial Data input (D). The instruction is terminated by driving Chip Select (S) high at a

byte boundary of the input data. The self-timed Write cycle, triggered by the rising edge of

Chip Select (S), continues for a period tW (as specified in Table 13 to Table 20). After this

time, the Write in Progress (WIP) bit is reset to 0.

In the case of Figure 12, Chip Select (S) is driven high after the eighth bit of the data byte

has been latched in, indicating that the instruction is being used to write a single byte. If,

though, Chip Select (S) continues to be driven low, as shown in Figure 13, the next byte of

input data is shifted in, so that more than a single byte, starting from the given address

towards the end of the same page, can be written in a single internal Write cycle. If Chip

Select (S) still continues to be driven low, the next byte of input data is shifted in, and used to

overwrite the byte at the start of the current page.

The instruction is not accepted, and is not executed, under the following conditions:

●

if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable

instruction just before)

●

if a Write cycle is already in progress

●

if the device has not been deselected, by Chip Select (S) being driven high, at a byte

boundary (after the rising edge of Serial Clock (C) that latches the last data bit, and

before the next rising edge of Serial Clock (C) occurs anywhere on the bus)

●

if Write Protect (W) is low or if the addressed page is in the area protected by the Block

Protect (BP1 and BP0) bits

Note:

The self-timed write cycle tW is internally executed as a sequence of two consecutive

events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is

read as “0” and a programmed bit is read as “1”.

Figure 12.

Byte Write (WRITE) sequence

Depending on the memory size, as shown in Table 6, the most significant address bits are Don’t Care.

AI01442D

3456789 10 11 12 13 14 15 16 17 18 19

A6 A5 A4 A3 A2 A1 A0

20 21 22 23

High Impedance

Instruction

Byte Address

765432

Data Byte

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